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參數(shù)資料
| 型號(hào)： | sda 5649x |
| 廠商： | SIEMENS AG |
| 英文描述： | VPS-Decoder(VPS解碼器) |
| 中文描述： | 車輛定位系統(tǒng)解碼器（車輛定位系統(tǒng)解碼器） |
| 文件頁數(shù)： | 6/26頁 |
| 文件大?。?/td> | 479K |
| 代理商： | SDA 5649X |
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SDA 5649
SDA 5649X
Semiconductor Group
49
I
2
C-Bus
General Information
The
I
2
C-Bus interface implemented on the PDC decoder is a slave transmitter/receiver, i.e., both
reading from and writing to the PDC / VPS decoder is possible. The clock line SCL is controlled only
by the bus master usually being a micro controller, whereas the SDA line is controlled either by the
master or by the slave. A data transfer can only be initiated by the bus master when the bus is free,
i.e., both SDA and SCL lines are in a high state. As a general rule for the
I
2
C-Bus, the SDA line
changes state only when the SCL line is low. The only exception to that rule are the Start Condition
and the Stop Condition. Further Details are given below. The following abbreviations are used:
START :
AS :
AM :
NAM :
STOP :
Start Condition generated by master
Ackknowledge by slave
Ackknowledge by master
No Ackknowledge by master
Stop Condition generated by master
Chip Address
There are two pairs of chip addresses, which are selected by the CS0-input pin according to the
following table:
Write Mode
For writing to the PDC decoder, the following format has to be used.
Data Transfer (Write Mode)
Step1 In order to start a data transfer the master generates a Start Condition on the bus by pulling
the SDA line low while the SCL line is held high.
Step 2 The bus master puts the chip address on the SDA line during the next eight SCL pulses.
Step 3 The master releases the SDA line during the ninth clock pulse. Thus the slave can generate
an acknowledge (AS) by pulling the SDA line to a low level.
Step 4 The controller transmits the data byte to set the Control register.
Step 5 The slave acknowledges the reception of the byte.
Step 6 The master concludes the data communication by generating a Stop Condition.
The write mode is used to set the
I
2
C-Bus control register which determines the operating mode:
CS0 Input
Write Mode
Read Mode
Low
20 (hex)
21 (hex)
High
22 (hex)
23 (hex)
START
Chipadress Write Mode
AS
Byte Set Control Register
AS
STOP
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| sda 5649 | VPS-Decoder(VPS解碼器) |
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| SDA6310 | DSR QPSK-Demodulator |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SDA5650 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:VPS / PDC-plus Decoder |
| SDA5650X | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:VPS / PDC-plus Decoder |
| SDA6000 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:Teletext Decoder with Embedded 16-bit Controller |
| SDA601 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:TSG 601 Serial Component Generator, SDA 601 Serial Digital Analyzer |
| SDA6102-5XGEG | 制造商:Siemens 功能描述:ELECTRONIC COMPONENT |
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