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參數(shù)資料
| 型號： | SD-15900PH-11 |
| 廠商： | DATA DEVICE CORP |
| 元件分類： | 位置變換器 |
| 英文描述： | SYNCHRO OR RESOLVER TO DIGITAL CONVERTER, CPGA85 |
| 封裝： | 1.120 X 1.120 INCH, 0.110 INCH HEIGHT, CERAMIC, PGA-85 |
| 文件頁數(shù)： | 2/8頁 |
| 文件大小： | 190K |
| 代理商： | SD-15900PH-11 |
2
PARAMETER
UNIT
VALUE
V
mA
Bits
LSB
1.39
V
pF
A
°C
V
±%
mA
-0.5 to +7.0
-0.5 to Vcc + 0.5
± 20
ACCURACY (ELECTRICAL)
SD-15900 alone
THEORY OF OPERATION
The two-speed synchro/resolver combiner is a completely self-
contained, real time, mathematically-based processing device.
The combiner accepts two-speed coarse/fine synchro/resolver
binary angular information from any two S/D converters such as
DDC’s RDC-19220 Series or the two-channel SD-14620 Series
and generates a composite binary angular output word up to 22
bits. All of the required timing and control signals for the two
external synchro/resolver converters are generated by the SD-
15900.
COMBINER OPERATION
FIGURE 1 is the functional block diagram of the SD-15900
series. The combiner is made up of three main sections: an input
front-end, a high resolution digital scaler, and timing and control.
The front-end consists of an Input Latch for both coarse and fine
data inputs, and a Digital Combiner with misalignment detection
and correction. Coarse and fine data are presented to the
Combiner via input port IN<1:8>. The fine data word is loaded
as two separate bytes. Control signals COARSE, FINELO, and
FINEHI are used to strobe in the data. The input data is then
latched and combined into a single word. Misalignment between
the coarse and fine input data is detected at this point and the
coarse corrected.
NOTE: The maximum detected misalignment will depend on the
target combiner speed ratio. Refer to TABLE 2.
The SD-15900XG can be programmed to binary ratios of 1 x 4,
8, 16, 32, and 64. Program inputs A, B and C as per TABLE 3.
1.195 x 1.195 x 0.185
(30.35 x 30.35 x 4.70)
0.28
(8)
1.12 x 1.12 x 0.110
(28.45 x 28.45 x 2.79)
0.21
(6)
0 to +70
-55 to +125
-65 to +150
Total Device
+5
5
20 (max)
POWER SUPPLIES
Nominal Voltage
Voltage Tolerance
Static Current (IDD)
TABLE 1. SD-15900 SPECIFICATIONS
ABSOLUTE MAXIMUM
RATINGS
DC Supply Voltage (Vcc)
Input Voltage
Output Voltage
I/O Sink/Source Current
(See NOTE)
RESOLUTION1
1 x 36
DIGITAL INPUT/OUTPUT
Logic Type
Inputs
Outputs
-30X
-10X
I/O Capacitance
Leakage Current
TTL/CMOS compatible
Logic 0 = -0.3 min to
0.8 max
Logic 1 = 2.0 min to
power supply
+0.3 max
Logic 0 = 0.5 max
@ 10 mA
Logic 1 = 2.4 min
@ -10 mA
Logic 0 = 0.4 max
@ 6 mA
Logic 1 = 3.7 min
@-4 mA
10
(Output = 0 V, F = 1 MHz)
±10 max
TEMPERATURE RANGE
Operating
-30X
-10X
Storage
NOTE: The device inputs are normally high impedance and draw
extremely low current. However, when input voltage is greater than
Vcc + 0.5 V or less than GND - 0.5V, the internal protection diode
will be forward biased and can draw excessive current.
TABLE 2. MISALIGNMENT VS. SPEED RATIO
SPEED RATIO
MAXIMUM MISALIGNMENT
72 - 63 x 1
64 - 33 x 1
32 - 17 x 1
16 - 9 x 1
8 - 5 x 1
4 - 3 x 1
1.25 degrees
2.5 degrees
5.625 degrees
11.25 degrees
22.5 degrees
45.0 degrees
TABLE 3. SD-15900XG PIN PROGRAMMABLE BINARY RATIOS
INPUT
RATIO
A
B
C
0
1
0
1
X
0
1
X
0
1
4 x 1
8 x 1
16 x 1
32 x 1
64 x 1
PHYSICAL
CHARACTERISTICS
SD-15900JX-30X
(Plastic J-lead)
Package Size
Weight
SD-15900GX-10X
(Ceramic PGA)
Package Size
Weight
in
(mm)
oz
(g)
in
(mm)
oz
(g)
Number of bits based on a
16-bit resolution of fine
S/D channel (up to 21 bits).
1. Please contact factory for other ratios.
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