AC CHARACTERISTICS
參數(shù)資料
型號： SCC68692E1N40,602
廠商： NXP Semiconductors
文件頁數(shù)： 26/28頁
文件大?。?/td> 0K
描述： IC DUART 40DIP
標準包裝： 9
特點： 故障啟動位檢測
通道數(shù)： 2，DUART
FIFO's： 3 位
電源電壓： 5V
帶并行端口： 是
帶自動流量控制功能： 是
帶故障啟動位檢測功能： 是
帶CMOS： 是
安裝類型： 通孔
封裝/外殼： 40-DIP（0.600"，15.24mm）
供應(yīng)商設(shè)備封裝： 40-DIP
包裝： 管件
其它名稱： 935027050602
SCC68692E1N40
SCC68692E1N40-ND
Philips Semiconductors
Product data
SCC68692
Dual asynchronous receiver/transmitter (DUART)
2004 Mar 03
7
AC CHARACTERISTICS1, 2, 4
SYMBOL
FIGURE
PARAMETER
LIMITS
UNIT
SYMBOL
FIGURE
PARAMETER
Min
Typ3
Max
UNIT
Reset Timing
tRES
1
RESET pulse width
200
–
ns
Bus Timing5
tAS
4,5,6
A1–A4 set-up time to CSN LOW
10
–
ns
tAH
4,5,6
A1–A4 hold time from CSN LOW
100
–
ns
tRWS
4,5,6
RWN set-up time to CSN HIGH
0
–
ns
tRWH
4,5,6
RWN holdup time to CSN HIGH
0
–
ns
tCSW8
4,5,6
CSN HIGH pulse width
160
–
ns
tCSD9
4,5,6
CSN or IACKN HIGH from DTACKN LOW
20
–
ns
tDD
4,5,6
Data valid from CSN or IACKN LOW
–
175
ns
tDA8
4
RDN LOW to data bus active
15
–
ns
tDF8
4,5,6
Data bus floating from CSN or IACKN HIGH
–
125
ns
tDI8
4
RDN HIGH to data bus invalid
20
–
ns
tDS
4,5,6
Data set-up time to CLK HIGH
100
–
ns
tDH
4,5,6
Data hold time from CSN HIGH
0
–
ns
tDAL
4,5,6
DTACKN LOW from read data valid
0
–
ns
tDCR
4,5,6
DTACKN LOW (read cycle) from CLK HIGH
–
125
ns
tDCW
4,5,6
DTACKN LOW (write cycle) form CLK HIGH
–
125
ns
tDAH
4,5,6
DTACKN HIGH from CSN or IACKN HIGH
–
100
ns
IDAT
4,5,6
DTACKN high-impedance from CSN or IACKN HIGH
–
125
ns
tCSC7
4,5,6
CSN or IACKN set-up time to clock HIGH
90
–
ns
Port Timing5
tPS
7
Port input set-up time to CSN LOW
0
–
ns
tPH
7
Port input hold time from CSN HIGH
0
–
ns
tPD
7
Port output valid from CSN HIGH
–
400
ns
Interrupt Timing
tIR10
6
INTRN (or OP3–OP7 when used as interrupts) negated from:
Read RHR (RxRDY/FFULL interrupt)
–
300
ns
Write THR (TxRDY interrupt)
–
300
ns
Reset command (break interrupt)
–
300
ns
Stop C/T command (counter interrupt)
–
300
ns
Read IPCR (input port change interrupt)
–
300
ns
Write IMR (clear of interrupt mask bit)
–
300
ns
Clock Timing
tCLK
7
X1/CLK HIGH or LOW time
100
–
ns
fCLK11
7
X1/CLK frequency
0
3.6864
4
MHz
tCTC
7
CTCLK (IP2) HIGH or LOW time
100
–
ns
fCTC9
7
CTCLK (IP2) frequency
100
–
4
MHz
tRX
7
RxC HIGH or LOW time
220
–
ns
fRX9
7
RxC frequency (16X)
(1X)
100
–
2
1
MHz
tTX
7
TxC HIGH or LOW time
220
–
ns
fTX9
7
TxC frequency (16X)
(1X)
0
–
2
1
MHz
Transmitter Timing
tTXD
8
TxD output delay from TxC external clock input on IP pin
–
350
ns
tTCS
8
Output delay from TxC LOW at OP pin to TxD data output
–
150
ns
Receiver Timing
tRXS
9
RxD data set-up time before RxC HIGH at external clock input on IP pin
240
–
ns
tRXH
9
RxD data hold time after RxC HIGH at external clock input on IP pin
200
–
ns
NOTES:
1. Parameters are valid over specified temperature range.
2. All voltage measurements are referenced to ground (GND). For testing, all inputs swing between 0.4 V and 2.4 V with a transition time of
5 ns maximum. For X1/CLK this swing is between 0.4 V and 4.4 V. All time measurements are referenced at input voltages of 0.8 V and
2.0 V and output voltages of 0.8 V and 2.0 V, as appropriate.
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