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參數(shù)資料
| 型號： | SCANPSC110F |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | SCAN Bridge Hierarchical and Multidrop Addressable JTAG Port(掃描橋分層多點可設(shè)定地址的JTAG端口) |
| 中文描述： | 掃描橋?qū)哟魏投帱c尋址JTAG端口（掃描橋分層多點可設(shè)定地址的的JTAG端口） |
| 文件頁數(shù)： | 14/29頁 |
| 文件大?。?/td> | 459K |
| 代理商： | SCANPSC110F |
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Level 2 Protocol
(Continued)
Register Descriptions
Instruction Register
The instruction shift register is an 8-bit register that is in se-
ries with the scan chain whenever the TAP Controller of the
SCANPSC110F Bridge is in the Shift-IR state. Upon exiting
the Capture-IRstate, the value “XXXXXX01” is captured into
the instruction register, where “XXXXXX” represents the
value on the S
(0–5)
inputs.
When the ’PSC110F controller is in the Wait-For-Address
state, the instruction register is used for ’PSC110F selection
via address matching. In addressing individual ’PSC110Fs,
the chip’s addressing logic performs a comparison between
a statically-configured (hard-wired) value on that ’PSC110F’s
slot inputs, and an address which is scanned into the chip”s
instruction register. Binary address codes “000000” through
“111010” (“00” through “3A” Hex) are reserved for address-
ing individual ’PSC110Fs. Address “3B” Hex is for Broadcast
mode.
In doing multi-cast (group) addressing, a scanned-in address
is compared against the (previously scanned-in) contents of
a ’PSC110F’s Multi-Cast Group register. Binary address
codes “111110” through “111111” (“3A” through “3F” Hex) are
reserved for multi-cast addressing, and should not be as-
signed as ’PSC110F slot-input values.
Boundary-Scan Register
The boundary-scan register is a “sample only” shift register
containing cells from the S
and OE inputs. The register
allows testing of circuitry external to the ’PSC110F. It permits
the signals flowing between the system pins to be sampled
and examined without interfering with the operation of the
on-chip system logic.
The scan chain is arranged as follows:
TDI
B
→
OE
→
S
5
→
S
4
→
S
3
→
S
2
→
S
1
→
S
0
→
LSPN
→
TDO
B
Bypass Register
The bypass register is a 1-bit register that operates as speci-
fied in IEEE Std. 1149.1 once the ’PSC110F has been se-
lected. The register provides a minimum length serial path
for the movement of test data between TDI
and the LSPN.
This path can be selected when no other test data register
needs to be accessed during a board-level test operation.
Use of the bypass register shortens the serial access-path to
test data registers located in other components on a
board-level test data path.
Multi-Cast Group Register
“Multi-cast” is a method of simultaneously communicating
with more than one selected ’PSC110F.
The multi-cast group register (MCGR) is a 2-bit register used
to determine which multi-cast group a particular ’PSC110F is
assigned to. Four addresses are reserved for multi-cast ad-
dressing. When a ’PSC110F is in the Wait-For-Addressstate
and receives a multi-cast address, and if that ’PSC110F’s
MCGR contains a matching value for that multi-cast ad-
dress, the ’PSC110F becomes selected and is ready to re-
ceive Level 2 Protocol (i.e., further instructions).
The MCGR is initialized to “00” upon entering the
Test-Logic-Reset state.
The following actions are used to perform multi-cast ad-
dressing:
1.
Assign all target ’PSC110Fs to a multi-cast group by
writing each individual target ’PSC110F’s MCGR with
the same multi-cast group code (see Table 6). This con-
figuration step must be done by individually addressing
each target ’PSC110F, using that chip’s assigned slot
value.
2.
Scan out the multi-cast group address through the TDI
B
input of all ’PSC110Fs. Note that this occurs in parallel,
resulting in the selection of only those ’PSC110Fs whose
MCGR was previously programmed with the matching
multi-cast group code.
TABLE 6. Multi-Cast Group Register Addressing
MCGR
Bits 1, 0
00
01
10
11
Hex Address
Binary Address
3C
3D
3E
3F
XX111100
XX111101
XX111110
XX111111
DS100327-11
FIGURE 10. Local Scan Port Synchronization from Parked-RTI State
S
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| SCANPSC110FDMQB | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:SCAN Bridge Hierarchical and Multidrop Addressable JTAG Port (IEEE1149.1 System Test Support) |
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| SCANPSC110FLMQB | 功能描述:IC BRIDGE LCC SCAN MUL JTAG PORT RoHS:否 類別:集成電路 (IC) >> 接口 - 專用 系列:* 標(biāo)準(zhǔn)包裝:3,000 系列:- 應(yīng)用:PDA，便攜式音頻/視頻，智能電話 接口:I²C，2 線串口 電源電壓:1.65 V ~ 3.6 V 封裝/外殼:24-WQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:24-QFN 裸露焊盤（4x4） 包裝:帶卷 (TR) 安裝類型:表面貼裝 產(chǎn)品目錄頁面:1015 (CN2011-ZH PDF) 其它名稱:296-25223-2 |
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