參數(shù)資料
型號: SCAN921260UJB
廠商: NATIONAL SEMICONDUCTOR CORP
元件分類: 通用總線功能
英文描述: X6 1:10 Deserializer with IEEE 1149.1 (JTAG) and at-speed BIST
中文描述: HEX LINE RECEIVER, PBGA196
封裝: LBGA-196
文件頁數(shù): 5/16頁
文件大?。?/td> 379K
代理商: SCAN921260UJB
Control Pins Truth Table
PWRDN
H
REN
H
SEL2
L
SEL1
L
SEL0
L
Rout
CHTST
Din0 (not
decoded)
LOCK[0:5]
Active(Note 9)
RCLK[0:5]
Active(Notes 10,
11)
Din6 Decoded to
Rout 0 (0:9)(Note
11)
Din6 Decoded to
Rout 1 (0:9)(Note
11)
Din6 Decoded to
Rout 2 (0:9)(Note
11)
Din6 Decoded to
Rout 3 (0:9)(Note
11)
Din6 Decoded to
Rout 4 (0:9)(Note
11)
Din6 Decoded to
Rout 5 (0:9)(Note
11)
Din6 is not
Decoded
Din6 is not
Decoded
Z
Z
H
H
L
L
H
Din1 (not
decoded)
Active(Note 9)
Active(Notes 10,
11)
H
H
L
H
L
Din2 (not
decoded)
Active(Note 9)
Active(Notes 10,
11)
H
H
L
H
H
Din3 (not
decoded)
Active(Note 9)
Active(Notes 10,
11)
H
H
H
L
L
Din4 (not
decoded)
Active(Note 9)
Active(Notes 10,
11)
H
H
H
L
H
Din5 (not
decoded)
Active(Note 9)
Active(Notes 10,
11)
H
H
H
H
L
Z
Active(Note 9)
Active(Notes 10,
11)
Active(Notes 10,
11)
Z
Z
H
H
H
H
H
Din6 (not
decoded)
Z
Z
Active(Note 9)
L
H
X
L
X
X
X
X
X
X
Z
Active(Note 9)
Note 8:
The routing of the Din inputs to the Deserializers and to the CHTST outputs are dependent on the states of SEL [0:2].
Note 9:
LOCK Active indicates that the LOCK output will reflect the state of it’s respective Deserializer with regard to the selected data stream.
Note 10:
RCLK Active indicates that the RCLK will be running if the Deserializer is locked.
Note 11:
Rout n[0:9] and RCLK [0:5] are Tri-Stated when LOCKn[0:5] is High.
Timing Diagrams
20014704
FIGURE 1. Deserializer Delay t
DD
S
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