參數(shù)資料
型號: SCAN921260UJB
廠商: NATIONAL SEMICONDUCTOR CORP
元件分類: 通用總線功能
英文描述: X6 1:10 Deserializer with IEEE 1149.1 (JTAG) and at-speed BIST
中文描述: HEX LINE RECEIVER, PBGA196
封裝: LBGA-196
文件頁數(shù): 3/16頁
文件大?。?/td> 379K
代理商: SCAN921260UJB
Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise
specified(Note 2) (Continued)
Symbol
Timing Requirements for REFCLK
t
RFCP
REFCLK Period
t
RFDC
REFCLK Duty Cycle
t
RFCP
/t
TCP
Ratio of REFCLK to TCLK
t
RFTT
REFCLK Transition Time
Deserializer Switching Characteristics
t
RCP
RCLK Period
t
RDC
RCLK Duty Cycle
Period of Bus LVDS signal when
CHTST is selected by MUX
CMOS/TTL Low-to-High
Transition Time
CMOS/TTL High-to-Low
Transition Time
t
ROS
Rout Data Valid before RCLK
t
ROH
Rout Data Valid after RCLK
t
HZR
High to TRI-STATE Delay
t
LZR
Low to TRI-STATE Delay
t
ZHR
TRI-STATE to High Delay
t
ZLR
TRI-STATE to Low Delay
Parameter
Conditions
Min
Typ
Max
Units
15.15
40
0.95
50
60
1.05
8
ns
%
50
ns
RCLK
RCLK (Note 7)
15.15
45
50
55
ns
%
50
t
CHTST
CHTST (Note 6)
25
ns
t
CLH
C
L
= 15pF
1.7
6
ns
t
CHL
C
L
= 15pF
1.6
6
ns
C
L
= 15pF,
Figure 2
C
L
= 15pF,
Figure 2
0.35*t
RCP
-0.35*t
RCP
ns
ns
ns
ns
ns
ns
C
L
= 15pF,
Figure 7
12
12
12
12
t
DD
Deserializer Delay
Figure 1
1.75*t
RCP
+3
1.75*t
RCP
+7
1.75*t
RCP
+10.5
2
10
1.5
5
+400
ns
t
DSR1
Deserializer PLL LOCK Time
from PWRDN (with SYNCPAT)
Figure 3
(Note 4)
66Mhz
20Mhz
66Mhz
20Mhz
us
us
us
us
ps
ps
t
DSR2
Deserializer PLL Lock Time from
SYNCPAT
Ideal Strobe Window Right
Ideal Strobe Window Left
Figure 4
(Note 4)
66Mhz,
Figure 10
66Mhz,
Figure 10
t
RNMI-R
t
RNMI-L
-400
Note 1:
“Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices
should be operated at these limits. The table of “Electrical Characteristics” specifies conditions of device operation.
Note 2:
Typical values are given for Vcc = 3.3V and TA =25C
Note 3:
Current into the device pins is defined as positive. Current out of device pins is defined as negative. Voltage are referenced to ground except VOD, VTH
and VTL which are differential voltages.
Note 4:
For the purpose of specifying deserializer PLL performance t
DSR1
and t
DSR2
are specified with the REFCLK running and stable, and specific conditions of
the incoming data stream (SYNCPATs). t
DSR1
is the time required for the deserializer to indicate lock upon power-up or when leaving the power-down mode. t
DSR2
is the time required to indicate lock for the powered-up and enabled deserializer when the input (RI+ and RI) conditions change from not receiving data to receiving
synchronization patterns (SYNCPATs). The time to lock to random data is dependent upon the incoming data.
Note 5:
t
RNM
is a measure of how much phase noise (jitter)the deserializer can tolerate in the incoming data stream before bit errors occur. The Deserializer Noise
Margin is Guaranteed By Design (GBD) using statistical analysis.
Note 6:
Because the Bus LVDS serial data stream is not decoded, the maximum frequency of the CHTST output driver could be exceeded if the data stream were
switched to CHTST. The maximum frequency of the BUS LVDS input should not exceed the parallel clock rate.
Note 7:
Guaranteed By Design (GBD) using statistical analysis.
S
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