參數(shù)資料
型號: SCAN1837TSSC
廠商: Fairchild Semiconductor Corporation
英文描述: Transparent Latch with 3-STATE Outputs
中文描述: 透明鎖存器與三態(tài)輸出
文件頁數(shù): 10/12頁
文件大?。?/td> 99K
代理商: SCAN1837TSSC
www.fairchildsemi.com
10
S
AC Operating Requirements
Scan Test Operation
Note 11:
Voltage Range 5.0 is 5.0V
±
0.5V.
Note 12:
This delay represents the timing relationship between the data input and TCK at the associated scan cells numbered 0-8, 9-17, 18-26 and 27-35.
Note 13:
Timing pertains to BSR 38 and 41 only.
Note 14:
This delay represents the timing relationship between AOE/BOE and TCK for scan cells 36 and 39 only.
Note 15:
Timing pertains to BSR 37 and 40 only.
Note:
All Input Timing Delays involving TCK are measured from the rising edge of TCK.
Symbol
Parameter
V
CC
T
A
=
+
25
°
C
C
L
=
50 pF
Guaranteed Minimum
T
A
=
40
°
C to
+
85
°
C
C
L
=
50 pF
Units
(V)
(Note 11)
t
S
Setup Time,
5.0
3.0
3.0
ns
Data to TCK (Note 12)
Hold Time,
TCK to Data (Note 12)
t
H
5.0
4.5
4.5
ns
t
S
Setup Time, H or L
AOE
1
, BOE
1
to TCK (Note 13)
Hold Time, H or L
5.0
3.0
3.0
ns
t
H
5.0
4.5
4.5
ns
TCK to AOE
1
, BOE
1
(Note 13)
Setup Time, H or L
Internal AOE, BOE,
t
S
5.0
3.0
3.0
ns
to TCK (Note 14)
Hold Time, H or L
TCK to Internal
t
H
5.0
3.0
3.0
ns
AOE, BOE (Note 14)
Setup Time
ALE, BLE (Note 15) to TCK
t
S
5.0
3.0
3.0
ns
t
H
Hold Time
TCK to ALE, BLE (Note 15)
Setup Time, H or L
5.0
3.5
3.5
ns
t
S
5.0
8.0
8.0
ns
TMS to TCK
Hold Time, H or L
TCK to TMS
t
H
5.0
2.0
2.0
ns
t
S
Setup Time, H or L
TDI to TCK
5.0
4.0
4.0
ns
t
H
Hold Time, H or L
TCK to TDI
Pulse Width TCK
5.0
4.5
4.5
ns
t
W
5.0
H
L
15.0
5.0
15.0
5.0
ns
f
MAX
Maximum TCK
5.0
25
25
MHz
Clock Frequency
Wait Time, Power Up to TCK
Power Down Delay
T
pu
T
dn
5.0
0.0
100
100
100
100
ns
ms
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