參數(shù)資料
型號： SCAN182541A
廠商： Fairchild Semiconductor Corporation
英文描述： Non-Inverting Line Driver with 25ohm Series Resistor Outputs
中文描述： 非反相線與25ohm系列電阻輸出驅(qū)動
文件頁數(shù)： 9/11頁
文件大小： 95K
代理商： SCAN182541A
9
www.fairchildsemi.com
S
DC Electrical Characteristics
(Continued)
Note 3:
Guaranteed not tested.
AC Electrical Characteristics
Normal Operation:
Note 4:
Voltage Range 5.0V
±
0.5V
Symbol
Parameter
V
CC
Min
Typ
Max
Units
Conditions
I
CCH
Power Supply Current
Max
250
μ
A
V
OUT
=
V
CC
; TDI, TMS
=
V
CC
Max
1.0
mA
V
OUT
=
V
CC
; TDI, TMS
=
GND
I
CCL
Power Supply Current
Max
65
mA
V
OUT
=
LOW; TDI, TMS
=
V
CC
Max
65.8
mA
V
OUT
=
LOW; TDI, TMS
=
GND
I
CCZ
Power Supply Current
Max
250
μ
A
TDI, TMS
=
V
CC
Max
1.0
mA
TDI, TMS
=
GND
I
CCT
Additional I
CC
/Input
All Other Inputs
Max
2.9
mA
V
IN
=
V
CC
2.1V
TDI, TMS Inputs
Max
3
mA
V
IN
=
V
CC
2.1V
I
CCD
Dynamic I
CC
No Load
Max
0.2
mA/
Outputs Open
MHz
One Bit Toggling, 50% Duty Cycle
Symbol
Parameter
V
CC
T
A
=
40
°
C to
+
85
°
C
C
L
=
50 pF
Typ
3.4
4.1
5.2
Units
(V)
(Note 4)
5.0
Min
1.0
1.9
2.0
Max
5.2
6.5
8.7
t
PLH
t
PHL
t
PLZ
t
PHZ
t
PZL
t
PZH
t
PLH
t
PHL
t
PLZ
t
PHZ
t
PZL
t
PZH
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PLZ
t
PHZ
t
PLZ
t
PHZ
t
PLZ
t
PHZ
t
PZL
t
PZH
t
PZL
t
PZH
t
PZL
t
PZH
Propagation Delay
Data to Q
Disable Time
ns
5.0
ns
1.9
2.4
1.6
5.6
6.1
5.1
9.2
9.6
8.5
Enable Time
5.0
ns
Propagation Delay
TCK to TDO
Disable Time
5.0
3.2
4.5
2.5
6.0
7.6
5.8
9.4
11.3
9.9
ns
5.0
ns
TCK to TDO
Enable Time
TCK to TDO
3.7
4.9
3.1
7.4
8.6
6.7
11.8
12.9
10.7
5.0
ns
Propagation Delay
TCK to Data Out during Update-DR State
Propagation Delay
3.7
4.9
4.2
6.7
8.3
7.9
10.3
12.4
12.2
ns
5.0
ns
TCK to Data Out during Update-IR State
Propagation Delay
TCK to Data Out during Test Logic Reset State
5.0
5.3
5.0
6.2
9.2
9.4
10.9
13.8
14.6
16.4
ns
5.0
Disable Time
TCK to Data Out during Update-DR State
Disable Time
3.7
4.3
3.7
7.9
8.7
8.5
13.0
13.7
14.2
ns
5.0
ns
TCK to Data Out during Update-IR State
Disable Time
TCK to Data Out during Test Logic Reset State
5.0
4.3
4.7
5.5
9.4
10.1
10.9
14.8
16.6
17.3
ns
5.0
Enable Time
TCK to Data Out during Update-DR State
Enable Time
5.5
4.0
5.8
9.8
7.9
10.9
14.7
12.5
16.5
ns
5.0
ns
TCK to Data Out during Update-IR State
Enable Time
TCK to Data Out during Test Logic Reset State
5.0
4.3
6.6
4.9
9.0
12.5
10.5
14.4
19.1
16.9
ns
5.0
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