參數(shù)資料
型號: SCAN182541A
廠商: Fairchild Semiconductor Corporation
英文描述: Non-Inverting Line Driver with 25ohm Series Resistor Outputs
中文描述: 非反相線與25ohm系列電阻輸出驅(qū)動
文件頁數(shù): 3/11頁
文件大小: 95K
代理商: SCAN182541A
3
www.fairchildsemi.com
S
Description of BOUNDARY-SCAN Circuitry
The scan cells used in the BOUNDARY-SCAN register are
one of the following two types depending upon their loca-
tion. Scan cell TYPE1 is intended to solely observe system
data, while TYPE2 has the additional ability to control sys-
tem data.
Scan cell TYPE1 is located on each system input pin while
scan cell TYPE2 is located at each system output pin as
well as at each of the two internal active-high output enable
signals. AOE controls the activity of the A-outputs while
BOE controls the activity of the B-outputs. Each will acti-
vate their respective outputs by loading a logic high.
The BYPASS register is a single bit shift register stage
identical to scan cell TYPE1. It captures a fixed logic low.
Bypass Register Scan Chain Definition
Logic 0
SCAN182541A Product IDCODE
(32-Bit Code per IEEE 1149.1)
The INSTRUCTION register is an 8-bit register which cap-
tures the default value of 10000001 (SAMPLE/PRELOAD)
during the CAPTURE-IR instruction command. The benefit
of capturing SAMPLE/PRELOAD as the default instruction
during CAPTURE-IR is that the user is no longer required
to shift in the 8-bit instruction for SAMPLE/PRELOAD. The
sequence of: CAPTURE-IR
EXIT1-IR
UPDATE-IR will
update the SAMPLE/PRELOAD instruction. For more infor-
mation refer to the section on instruction definitions.
Instruction Register Scan Chain Definition
MSB
LSB
Scan Cell TYPE1
Scan Cell TYPE2
Version Entity
Part
Manufacture
r
ID
00000001111
Required b
y
1149.1
1
Number
0000
111111 000000100
1
MSB
LSB
Instruction Code
00000000
10000001
10000010
00000011
01000001
01000010
00100010
10101010
11111111
All Others
Instruction
EXTEST
SAMPLE/PRELOAD
CLAMP
HIGH-Z
SAMPLE-IN
SAMPLE-OUT
EXTEST-OUT
IDCODE
BYPASS
BYPASS
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