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參數(shù)資料
| 型號(hào)： | SCAN182374ASSCX |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | 總線收發(fā)器 |
| 中文描述： | SCAN/JTAG/3J SERIES, 9-BIT BOUNDARY SCAN MEMORY DRIVER, TRUE OUTPUT, PDSO56 |
| 封裝： | 0.300 INCH, MO-118, SSOP-56 |
| 文件頁(yè)數(shù)： | 5/12頁(yè) |
| 文件大?。?/td> | 103K |
| 代理商： | SCAN182374ASSCX |
www.fairchildsemi.com
2
SCAN18237
4A
Functional Description
The SCAN182374A consists of two sets of nine edge-trig-
gered flip-flops with individual D-type inputs and 3-STATE
true outputs. The buffered clock and buffered Output
Enable pins are common to all flip-flops. Each set of the
nine flip-flops will store the state of their individual D inputs
that meet the setup and hold time requirements on the
LOW-to-HIGH Clock (ACP or BCP) transition. With the
Output Enable (AOE1 or BOE1) LOW, the contents of the
nine flip-flops are available at the outputs. When the Output
Enable is HIGH, the outputs go to the high impedance
state. Operation of the Output Enable input does not affect
the state of the flip-flops.
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
Block Diagrams
Byte-A
Note: BSR stands for Boundary Scan Register
Tap Controller
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| SCAN182541_YBE3026B WAF | 制造商:Fairchild Semiconductor Corporation 功能描述: |
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