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參數(shù)資料
| 型號(hào)： | SCAN182245ASSCX |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | 總線收發(fā)器 |
| 中文描述： | SCAN/JTAG/3J SERIES, DUAL 9-BIT BOUNDARY SCAN TRANSCEIVER, TRUE OUTPUT, PDSO56 |
| 封裝： | 0.300 INCH, MO-118, SSOP-56 |
| 文件頁(yè)數(shù)： | 3/13頁(yè) |
| 文件大?。?/td> | 133K |
| 代理商： | SCAN182245ASSCX |
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www.fairchildsemi.com
SCAN18224
5A
AC Operating Requirements
Scan Test Operation
Note 7: Voltage Range 5.0V
± 0.5V
Note 8: Timing pertains to the TYPE1 BSR and TYPE2 BSR after the buffer (BSR 0–8, 9–17, 18–26, 27–35, 36–44, 45–53, 54–62, 63–71).
Note 9: Timing pertains to BSR 74 and 78 only.
Note 10: Timing pertains to BSR 75 and 79 only.
Note 11: Timing pertains to BSR 72, 73, 76 and 77 only.
Note: All Input Timing Delays involving TCK are measured from the rising edge of TCK.
Capacitance
Note 12: CI/O is measured at frequency f = 1 MHz, per MIL-STD-883B, Method 3012.
Symbol
Parameter
VCC
TA = 40°C to +85°C
Units
(V)
CL = 50 pF
(Note 7)
Guaranteed Minimum
tS
Setup Time
5.0
4.8
ns
Data to TCK (Note 8)
tH
Hold Time
5.0
2.5
ns
Data to TCK (Note 8)
tS
Setup Time, H or L
5.0
4.1
ns
G1, G2 to TCK (Note 9)
tH
Hold Time, H or L
5.0
1.7
ns
TCK to G1, G2 (Note 9)
tS
Setup Time, H or L
5.0
4.2
ns
DIR1, DIR2 to TCK (Note 10)
tH
Hold Time, H or L
5.0
2.3
ns
TCK to DIR1, DIR2 (Note 10)
tS
Setup Time
5.0
3.8
ns
Internal OE to TCK (Note 11)
tH
Hold Time, H or L
5.0
2.3
ns
TCK to Internal OE (Note 10)
tS
Setup Time, H or L
5.0
8.7
ns
TMS to TCK
tH
Hold Time, H or L
5.0
1.5
ns
TCK to TMS
tS
Setup Time, H or L
5.0
6.7
ns
TDI to TCK
tH
Hold Time, H or L
5.0
ns
TCK to TDI
tW
Pulse Width TCK:
H
5.0
10.2
ns
L8.5
fMAX
Maximum TCK
5.0
50
MHz
Clock Frequency
tPU
Wait Time,
5.0
100
ns
Power Up to TCK
tDN
Power Down Delay
0.0
100
ms
Symbol
Parameter
Typ
Units
Conditions, TA = 25°C
CIN
Input Capacitance
5.9
pF
VCC = 0.0V (Gn, DIRn)
CI/O (Note 12)
Output Capacitance
13.7
pF
VCC = 5.0V (An, Bn)
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