參數(shù)資料
型號: SCAN182245ASSC
廠商: FAIRCHILD SEMICONDUCTOR CORP
元件分類: 總線收發(fā)器
中文描述: SCAN/JTAG/3J SERIES, DUAL 9-BIT BOUNDARY SCAN TRANSCEIVER, TRUE OUTPUT, PDSO56
封裝: 0.300 INCH, MO-118, SSOP-56
文件頁數(shù): 2/13頁
文件大?。?/td> 133K
代理商: SCAN182245ASSC
www.fairchildsemi.com
10
SCAN18224
5A
AC Electrical Characteristics
Normal Operation:
Note 5: Voltage Range 5.0V
± 0.5V
AC Electrical Characteristics
Scan Test Operation
Note 6: Voltage Range 5.0V
± 0.5V
Note: All Propagation Delays involving TCK are measured from the falling edge of TCK.
Symbol
Parameter
VCC
TA = 40°C to +85°C
Units
(V)
CL = 50 pF
(Note 5)
Min
Typ
Max
tPLH
tPHL
Propagation Delay
5.0
1.0
3.1
5.2
ns
A to B, B to A
1.5
4.4
6.5
tPLZ
Disable Time
5.0
1.5
4.8
8.6
ns
tPHZ
1.5
5.2
8.9
tPZL
Enable Time
5.0
1.5
5.5
9.1
ns
tPZH
1.5
4.6
8.2
Symbol
Parameter
VCC
TA = 40°C to +85°C
Units
(V)
CL = 50 pF
(Note 6)
Min
Typ
Max
tPLH
tPHL
Propagation Delay
5.0
2.9
6.1
10.2
ns
TCK to TDO
4.2
7.7
12.1
tPLZ
Disable Time
5.0
2.1
5.9
10.7
ns
tPHZ
TCK to TDO
3.3
7.4
12.5
tPZL
tPZH
Enable Time
5.0
4.6
8.7
13.7
ns
TCK to TDO
2.8
6.8
11.5
tPLH
Propagation Delay
5.0
2.8
6.3
10.7
ns
tPHL
TCK to Data Out during Update-DR State
4.5
8.2
13.0
tPLH
Propagation Delay
5.0
3.3
7.2
12.2
ns
tPHL
TCK to Data Out during Update-IR State
5.0
9.3
14.8
tPLH
Propagation Delay
5.0
3.7
8.4
14.0
ns
tPHL
TCK to Data Out during Test Logic Reset State
5.7
10.8
17.2
tPLZ
Disable Time
5.0
2.8
7.6
13.9
ns
tPHZ
TCK to Data Out during Update-DR State
3.5
8.4
14.5
tPLZ
Disable Time
5.0
3.6
8.7
15.1
ns
tPHZ
TCK to Data Out during Update-IR State
3.8
9.2
15.9
tPLZ
Disable Time
5.0
4.0
9.8
17.1
ns
tPHZ
TCK to Data Out during Test Logic Reset State
4.2
9.9
16.6
tPZL
Enable Time
5.0
4.4
9.3
15.5
ns
tPZH
TCK to Data Out during Update-DR State
3.0
7.5
13.3
tPZL
Enable Time
5.0
5.2
10.7
17.4
ns
tPZH
TCK to Data Out during Update-IR State
3.9
9.0
15.4
tPZL
Enable Time
5.0
5.7
12.0
19.8
ns
tPZH
TCK to Data Out during Test Logic Reset State
3.0
10.2
17.6
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