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參數(shù)資料
| 型號： | SC68C94 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | nullQuad universal asynchronous receiver/transmitter QUART |
| 中文描述： | nullQuad通用異步接收器/發(fā)送器夸脫 |
| 文件頁數(shù)： | 27/33頁 |
| 文件大?。?/td> | 215K |
| 代理商： | SC68C94 |
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Philips Semiconductors
Product specification
SC68C94
Quad universal asynchronous receiver/transmitter (QUART)
1995 May 1
27
RESET
t
RES
SD00169
Figure 7. Reset Timing
RDN
CEN
I/O as Output
I/O as Input
t
PS
t
PH
t
PD
t
PD
WRN
OLD DATA
NEW DATA
I/O PINS MUST BE STABLE FOR NON-CHANGING BUS DATA DURING THE READ.
NOTE: I/O PIN DATA IS NOT LATCHED
SD00170
Figure 8. I/O Port Timing
WRN
INTERRUPT
1
OUTPUT
RDN
INTERRUPT
1
OUTPUT
V
M
t
IR
t
IR
V
OL
+0.5V
V
OL
+0.5V
V
OL
V
OL
NOTES:
1. INCLUDES I/O WHEN USED AS TxRDY or RxDY/FFULL OUTPUTS AS WELL AS IRQN.
2. THE TEST FOR OPEN DRAIN OUTPUTS IS INTENDED TO GUARANTEE SWITCHING OF THE OUTPUT TRANSISTOR. MEASUREMENT OF THIS RESPONSE IS
REFERENCED FROM THE MIDPOINT OF THE SWITCHING SIGNAL, V
, TO A POINT 0.5V ABOVE V
. THIS POINT REPRESENTS NOISE MARGIN THAT AS-
SURES TRUE SWITCHING HAS OCCURRED. BEYOND THIS LEVEL, THE EFFECTS OF EXTERNAL CIRCUITRY AND TEST ENVIRONMENT ARE PRONOUNCED
AND CAN GREATLY AFFECT THE RESULTANT MEASUREMENT.
SD00171
Figure 9. Interrupt Timing
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