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參數(shù)資料
| 型號(hào)： | SC68C94 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | nullQuad universal asynchronous receiver/transmitter QUART |
| 中文描述： | nullQuad通用異步接收器/發(fā)送器夸脫 |
| 文件頁(yè)數(shù)： | 25/33頁(yè) |
| 文件大?。?/td> | 215K |
| 代理商： | SC68C94 |
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Philips Semiconductors
Product specification
SC68C94
Quad universal asynchronous receiver/transmitter (QUART)
1995 May 1
25
AC ELECTRICAL CHARACTERISTICS
T
A
= 25
°
C; V
CC
= 5V
±
10%, unless otherwise specified. Limits shown as nn/nn refer to
Commercial/Industrial temperature range. Single numbers apply to both ranges.
NO.
FIGURE
CHARACTERISTIC
LIMITS
Typ
UNIT
Min
Max
110/115
90/122 + 3
X1 edges
1
30
30
1
3
D[7:0] Valid after IACKN Low
ns
2
3
DACKN Low after IACKN Low
10 + 2
X1 edges
1
0
0
110/115
ns
3
4
5
3
3
3
D[7:0] floating after IACKN High
DACKN High after IACKN High
IACKN High after IACKN Low
ns
ns
ns
NOTE:
1. Consecutive write operations to the upper four bits of the Command Register (CR) require at least three X1/CLK edges; four X1/CLK edges
in the ‘X1/CLK divide by 2 edges’ according to register 2E or 2F setting.
IRQN
IACKN
D[7:0]
DACKN
1
5
2
3
4
SD00165
NOTE: Rise time of IRQN is dependent on external circuit.
Figure 3. Interrupt Knowledge (IACKN) Timing
OSC/N
EVAL/HOLD
IACKN
CIR
VALUE FOR THIS INTERRUPT
SD00182
Figure 4. Interrupt Bid Arbitration Timing
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