參數(shù)資料
型號: SC28L92A1BS,528
廠商: NXP Semiconductors
文件頁數(shù): 38/73頁
文件大?。?/td> 0K
描述: IC UART DUAL W/FIFO 44PQFP
標準包裝: 4,000
系列: IMPACT
特點: 故障啟動位檢測
通道數(shù): 2,DUART
FIFO's: 16 字節(jié)
電源電壓: 3.3V,5V
帶自動流量控制功能:
帶故障啟動位檢測功能:
帶調(diào)制解調(diào)器控制功能:
帶CMOS:
安裝類型: 表面貼裝
封裝/外殼: 48-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 48-HVQFN EP(6x6)
包裝: 帶卷 (TR)
其它名稱: 935281063528
SC28L92A1BS-F
SC28L92A1BS-F-ND
43
2552K–AVR–04/11
ATmega329/3290/649/6490
Figure 10-3. MCU Start-up, RESET Extended Externally
10.4
External Reset
An External Reset is generated by a low level on the RESET pin. Reset pulses longer than the
minimum pulse width (see “System and Reset Characteristics” on page 330) will generate a
reset, even if the clock is not running. Shorter pulses are not guaranteed to generate a reset.
When the applied signal reaches the Reset Threshold Voltage – V
RST – on its positive edge, the
delay counter starts the MCU after the Time-out period – t
TOUT – has expired.
Figure 10-4. External Reset During Operation
10.5
Brown-out Detection
ATmega329/3290/649/6490 has an On-chip Brown-out Detection (BOD) circuit for monitoring
the V
CC level during operation by comparing it to a fixed trigger level. The trigger level for the
BOD can be selected by the BODLEVEL Fuses. The trigger level has a hysteresis to ensure
spike free Brown-out Detection. The hysteresis on the detection level should be interpreted as
V
BOT+ = VBOT + VHYST/2 and VBOT- = VBOT - VHYST/2.
When the BOD is enabled, and V
CC decreases to a value below the trigger level (VBOT- in Figure
10-5), the Brown-out Reset is immediately activated. When V
CC increases above the trigger
level (V
BOT+ in Figure 10-5), the delay counter starts the MCU after the Time-out period tTOUT has
expired.
The BOD circuit will only detect a drop in V
CC if the voltage stays below the trigger level for lon-
ger than t
RESET
TIME-OUT
INTERNAL
RESET
t
TOUT
V
POT
V
RST
VCC
CC
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