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參數(shù)資料
型號(hào)： SC28C94A1A,512
廠商： NXP Semiconductors
文件頁(yè)數(shù)： 36/39頁(yè)
文件大?。?/td> 0K
描述： IC UART QUAD W/FIFO 52-PLCC
產(chǎn)品培訓(xùn)模塊： Stand-Alone UARTs
標(biāo)準(zhǔn)包裝： 23
特點(diǎn)： 故障啟動(dòng)位檢測(cè)
通道數(shù)： 4，QUART
FIFO's： 8 字節(jié)
電源電壓： 5V
帶自動(dòng)流量控制功能： 是
帶故障啟動(dòng)位檢測(cè)功能： 是
帶調(diào)制解調(diào)器控制功能： 是
帶CMOS： 是
安裝類(lèi)型： 表面貼裝
封裝/外殼： 52-LCC（J 形引線）
供應(yīng)商設(shè)備封裝： 52-PLCC（19.2x19.2）
包裝： 管件
產(chǎn)品目錄頁(yè)面： 828 (CN2011-ZH PDF)
其它名稱(chēng)： 568-3993-5
935262534512
SC28C94A1A
SC28C94A1A-ND
Philips Semiconductors
Product data sheet
SC28C94
Quad universal asynchronous receiver/transmitter (QUART)
2006 Aug 09
6
Table 1.
QUART Registers1
A5:0
READ (RDN = Low)
WRITE (WRN = Low)
000000
Mode Register a (MR0a, MR1a, MR2a)
000001
Status Register a (SRa)
Clock Select Register a (CSRa)
000010
Reserved
Command Register a (CRa)
000011
Receive Holding Register a (RxFIFOa)
Transmit Holding Register a (TxFIFOa)
000100
Input Port Change Reg ab (IPCRab)
Auxiliary Control Reg ab (ACRab)
000101
Interrupt Status Reg ab (ISRab)
Interrupt Mask Reg ab (IMRab)
000110
Counter/Timer Upper ab (CTUab)
Counter/Timer Upper Reg ab (CTURab)
000111
Counter/Timer Lower ab (CTLab)
Counter/Timer Lower Reg ab (CTLRab)
001000
Mode Register b (MR0b, MR1b, MR2b)
001001
Status Register b (SRb)
Clock Select Register b (CSRb)
001010
Reserved
Command Register b (CRb)
001011
Receive Holding Register b (RxFIFOb)
Transmit Holding Register b (TxFIFOb)
001100
Output Port Register ab (OPRab)
001101
Input Port Register ab (IPRab)
I/OPCRa (I/O Port Control Reg a)
001110
Start Counter ab
I/OPCRb (I/O Port Control Reg b)
001111
Stop Counter ab
Reserved
010000
Mode Register c (MR0c, MR1c, MR2c)
010001
Status Register c (SRc)
Clock Select Register c (CSRc)
010010
Reserved
Command Register c (CRc)
010011
Receive Holding Register c (RxFIFOc)
Transmit Holding Register c (TxFIFOc)
010100
Input Port Change Reg cd (IPCRcd)
Auxiliary Control Reg cd (ACRcd)
010101
Interrupt Status Reg cd (ISRcd)
Interrupt Mask Reg cd (IMRcd)
010110
Counter/Timer Upper cd (CTUcd)
Counter/Timer Upper Reg cd (CTURcd)
010111
Counter/Timer Lower cd (CTLcd)
Counter/Timer Lower Reg cd (CTLRcd)
011000
Mode Register d (MR0d, MR1d, MR2d)
011001
Status Register d (SRd)
Clock Select Register d (CSRd)
011010
Reserved
Command Register d (CRd)
011011
Receive Holding Register d (RxFIFOd)
Transmit Holding Register d (TxFIFOd)
011100
Output Port Register cd (OPRcd)
011101
Input Port Register cd (IPRcd)
I/OPCRc (I/O Port Control Reg c)
011110
Start Counter cd
I/OPCRd (I/O Port Control Reg d)
011111
Stop Counter cd
Reserved
100000
Bidding Control Register a (BCRa)
100001
Bidding Control Register b (BCRb)
100010
Bidding Control Register c (BCRc)
100011
Bidding Control Register d (BCRd)
100100
Reserved
Power Down
100101
Reserved
Power Up
100110
Reserved
Disable DACKN
100111
Reserved
Enable DACKN
101000
Current Interrupt Register (CIR)
Reserved
101001
Global Interrupting Channel Reg (GICR)
Interrupt Vector Register (IVR)
101010
Global Int Byte Count Reg (GIBCR)
Update CIR
101011
Global Receive Holding Reg (GRxFIFO)
Global Transmit Holding Reg (GTxFIFO)
101100
Interrupt Control Register (ICR)
101101
Reserved
BRG Rate. 00 = low; 01 = high
101110
Reserved
Set X1/CLK divide by two2 (use when X1 is
t 4 Mhz)
101111
Reserved
Set X1/CLK Normal2
110000–111000
Reserved
111001
Reserved
Test Mode
111010–111111
Reserved
NOTES:
1. Registers not explicitly reset by hardware reset power up randomly.
2. In X1/CLK divide by 2 all circuits receive the divided clock except the BRG and change-of-state detectors.
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