AC ELECTRIC" />
參數(shù)資料
型號： SC28C94A1A,512
廠商： NXP Semiconductors
文件頁數(shù)： 20/39頁
文件大?。?/td> 0K
描述： IC UART QUAD W/FIFO 52-PLCC
產(chǎn)品培訓(xùn)模塊： Stand-Alone UARTs
標準包裝： 23
特點： 故障啟動位檢測
通道數(shù)： 4，QUART
FIFO's： 8 字節(jié)
電源電壓： 5V
帶自動流量控制功能： 是
帶故障啟動位檢測功能： 是
帶調(diào)制解調(diào)器控制功能： 是
帶CMOS： 是
安裝類型： 表面貼裝
封裝/外殼： 52-LCC（J 形引線）
供應(yīng)商設(shè)備封裝： 52-PLCC（19.2x19.2）
包裝： 管件
產(chǎn)品目錄頁面： 828 (CN2011-ZH PDF)
其它名稱： 568-3993-5
935262534512
SC28C94A1A
SC28C94A1A-ND
Philips Semiconductors
Product data sheet
SC28C94
Quad universal asynchronous receiver/transmitter (QUART)
2006 Aug 09
27
AC ELECTRICAL CHARACTERISTICS4
VCC = 5V ± 10%, TA = –40 _C to +85 _C, unless otherwise specified.
NO
FIGURE
CHARACTERISTIC
LIMITS
UNIT
NO.
FIGURE
CHARACTERISTIC
Min
Typ
Max
UNIT
1
5
Setup: A[5:0] valid to CEN Low
10
ns
2
5
Hold: A[5:0] valid after CEN Low6
45
ns
3
5
Access: Later of CEN Low and RDN Low, to Dnn valid (read)
110/115
ns
4
5
Later of CEN Low and (RDN or WRN as applicable) Low, to DACKN Low
ns
Normal Operation:
10 + 2
X1 edges5
90/122 + 3
X1 edges5
From Power Down:
150
5
Earlier of CEN High or RDN High, to Dnn released (read)1
0
30
ns
6
5
Earlier of CEN High or (RDN or WRN as applicable) High, to DACKN released
0
30
ns
7
5
Earlier of CEN High or (RDN or WRN as applicable) High, in one cycle, to later
of CEN Low and (RDN or WRN as applicable) Low, for the next cycle
50
ns
8
5
Setup, Dnn valid (write) to later of CEN Low and WRN Low2
–30
ns
9
5
Later of CEN Low and WRN Low, to earlier of CEN High or WRN High
110/115
ns
10
5
Hold: Dnn valid (write) after DACKN Low, CEN High or WRN High3
0
ns
NOTES:
1. The minimum time indicates that read data will remain valid until the bus master drives CEN and/or RDN to High.
2. The fact that this parameter is negative means that the Dnn line may actually become valid after CEN and WRN are both Low.
3. In a Write operation, the bus master must hold the write data valid either until drives CEN and/or WRN to High, or until the QUART drives
DACKN to Low, whichever comes first.
4. Test condition for interrupt and I/O outputs: CL = 50 pF, forced current for VOL = 4.0 mA; forced current for VOH = 400 A, RL = 2.7 k to
VCC. Test condition for rest of outputs: CL = 150 pF
5. Consecutive write operations to the upper four bits of the Command Register (CR) require at least three X1/CLK edges; four X1/CLK edges
in the ‘X1/CLK divide by 2 edges’ according to register 2Eh or 2Fh setting.
6. Address is latched at leading edge of a read or write cycle.
A[5:0]
CEN
RDN
WRN
D[7:0]
12
1
2
READ CYCLE
WRITE CYCLE
DACKN
4
3
7
9
7
9
5
6
8
4
10
6
SD00677
X1/CLK
Figure 5. A Read Cycle Followed by a Write Cycle with DACKN
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