參數(shù)資料
型號: SC18IS600IBS
廠商: NXP SEMICONDUCTORS
元件分類: 總線控制器
英文描述: I2C BUS CONTROLLER, PQCC24
封裝: 4 X 4 MM, 0.85 MM HEIGHT, PLASTIC, MO-220, SOT616-3, HVQFN-24
文件頁數(shù): 4/30頁
文件大?。?/td> 164K
代理商: SC18IS600IBS
SC18IS600_601_5
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 05 — 28 July 2008
12 of 30
NXP Semiconductors
SC18IS600/601
SPI to I2C-bus interface
6.3 External clock input (SC18IS601)
In this device, the processor clock is derived from an external source driving the CLKIN
pin. The clock rate may be from 0 Hz up to 18 MHz.
6.4 I2C-bus serial interface
I2C-bus uses two wires (SDA and SCL) to transfer information between devices connected
to the bus, and it has the following features:
Bidirectional data transfer between masters and slaves
Multi-master bus (no central master)
Arbitration between simultaneously transmitting masters without corruption of serial
data on the bus
Serial clock synchronization allows devices with different bit rates to communicate via
one serial bus
Serial clock synchronization can be used as a handshake mechanism to suspend and
resume serial transfer
The I2C-bus may be used for test and diagnostic purposes.
A typical I2C-bus conguration is shown in Figure 11. The SC18IS600/601 device
provides a byte-oriented I2C-bus interface that supports data transfers up to 400 kHz.
(Refer to
UM10204, “I2C-bus specication and user manual”.)
6.5 Serial Peripheral Interface (SPI)
The host communicates with the SC18IS600/601 via the SPI interface. The
SC18IS600/601 operates in Slave mode up to 3 Mbit/s.
The SPI interface has four pins: SCLK, MOSI, MISO, and CS.
SCLK, MOSI and MISO are typically tied together between two or more SPI devices.
Data ows from the master to the SC18IS600/601 on the MOSI (Master Out Slave In)
pin and ows from SC18IS600/601 to the master on the MISO (Master In Slave Out)
pin. The SCLK signal is an input to the SC18IS600/601.
CS is the slave select pin. In a typical conguration, an SPI master selects one SPI
device as the current slave. An SPI slave device uses its CS pin to determine whether
it is selected. The CS pin may be tied LOW if it is the only device on the bus.
Typical connections are shown in Figure 12.
Fig 11. I2C-bus conguration
RPU
002aab716
VDD
SC18IS600/601
I2C-BUS
DEVICE
I2C-BUS
DEVICE
I2C-bus
SDA
SCL
RPU
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