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參數(shù)資料
| 型號： | SC16IS740IPW/Q900, |
| 廠商： | NXP Semiconductors |
| 文件頁數(shù)： | 3/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC UART SINGLE W/FIFO 16-TSSOP |
| 標準包裝： | 1 |
| 特點： | 低電流 |
| 通道數(shù)： | 1，UART |
| FIFO's： | 64 字節(jié) |
| 規(guī)程： | RS232，RS485 |
| 電源電壓： | 2.5V, 3.3V |
| 帶自動流量控制功能： | 是 |
| 帶故障啟動位檢測功能： | 是 |
| 帶調(diào)制解調(diào)器控制功能： | 是 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-TSSOP（0.173"，4.40mm 寬） |
| 供應商設備封裝： | 16-TSSOP |
| 包裝： | 標準包裝 |
| 其它名稱： | 568-6674-6 |
2006 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FIN324C Rev. 1.1.4
14
SerDes
FIN324C
—
24-Bit
Ultra-Low
Power
Serializer
/
Deserializer
Supporting
Single
and
Dual
Displays
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
tVDD-SKEW
Allowed Skew between VDDP
and VDDA/S
(18)
Figure 18
-∞
+∞
ms
tVDD-RES
Minimum Reset Low Time
After VDD Stable
M/S=0, /RES=
↑(19)
Figure 18
20
s
tRES-STBY
/STBY Wait Time After
/RES
↑
M/S=1 /RES=1, /STBY=
↑
Figure 18
20
s
tDVALID
/STBY to Active Edge of
Strobe
M/S=0 /RES=1
(20)
Figure 18
30
s
Notes:
4.
Active edge of strobe is the rising edge for a write transaction and the falling edge for a read transaction.
5.
Characterized, but not production tested.
6.
Indirectly tested through serial clock frequency and serial data bit tests.
7.
Pulse width low WCLKn measurements are measured at 30% of VDDP. Measurements apply when SLEW=0 or
SLEW=1.
8.
Minimum times occur with maximum oscillator frequency. Maximum times occur with minimum oscillator
frequency.
9.
Write latency is the sum of the delay through the master serializer and slave deserializer, plus the flight time
across the flex cable and I/O propagation delays.
10. Assumes propagation delay across the flex cable and through the I/Os of 20ns.
11. Total read latency tPD-RD is the sum of the Read-Control Phase latency (tPD-RDC) and the Read-Data Phase
latency (tPD-RDD). tPD-RD=tPD-RDC+ tPD-RDD.
12. Read-Control latency is the sum of the delay through the master serializer and slave deserializer, plus flex cable
flight times and I/O propagation delays.
13. Read Data latency is the sum of the delay through the slave serializer and master deserializer, plus flex cable
flight times and I/O propagation delays.
14. SPI-Write latency is the sum of the delay through the master serializer and slave deserializer, plus the flight time
across the flex cable and I/O propagation delays.
15. Timing allows the device to completely reset prior to powering down.
16. Internal reset filter allows assertion prior to completion of read or write date transfer.
17. Timing ensures that last write transaction is complete prior to going into standby.
18. VDDA/S must power up together. VDDP may power-up relative to VDDA/S in any order without static power being
consumed. Guaranteed by characterization.
19. /RES signal should be held low for minimum time specified after supplies go HIGH. It is recommended that
/RES be held low during the power supply ramp.
20. STRBn must be held off until internal oscillator has stabilized.
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