參數(shù)資料
型號(hào): SC16C754BIBM,151
廠商: NXP Semiconductors
文件頁(yè)數(shù): 18/50頁(yè)
文件大?。?/td> 0K
描述: IC UART QUAD W/FIFO 64-LQFP
產(chǎn)品培訓(xùn)模塊: Stand-Alone UARTs
標(biāo)準(zhǔn)包裝: 250
通道數(shù): 4,QUART
FIFO's: 64 字節(jié)
電源電壓: 2.5V,3.3V,5V
帶自動(dòng)流量控制功能:
帶故障啟動(dòng)位檢測(cè)功能:
帶調(diào)制解調(diào)器控制功能:
安裝類型: 表面貼裝
封裝/外殼: 64-LQFP
供應(yīng)商設(shè)備封裝: 64-LQFP(7x7)
包裝: 托盤
產(chǎn)品目錄頁(yè)面: 828 (CN2011-ZH PDF)
其它名稱: 568-3290
935279069151
SC16C754BIBM-S
SC16C754B_4
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 — 6 October 2008
25 of 51
NXP Semiconductors
SC16C754B
5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs
7.4 Line Control Register (LCR)
This register controls the data communication format. The word length, number of stop
bits, and parity type are selected by writing the appropriate bits to the LCR. Table 12
shows the line control register bit settings.
Table 12.
Line control register bits description
Bit
Symbol
Description
7
LCR[7]
Divisor latch enable.
logic 0 = divisor latch disabled (normal default condition)
logic 1 = divisor latch enabled
6
LCR[6]
Break control bit. When enabled, the Break control bit causes a break
condition to be transmitted (the TX output is forced to a logic 0 state). This
condition exists until disabled by setting LCR[6] to a logic 0.
logic 0 = no TX break condition (normal default condition)
logic 1 = forces the transmitter output (TX) to a logic 0 to alert the
communication terminal to a line break condition
5
LCR[5]
Set parity. LCR[5] selects the forced parity format (if LCR[3] = 1).
logic 0 = parity is not forced (normal default condition)
LCR[5] = logic 1 and LCR[4] = logic 0: parity bit is forced to a logic 1 for
the transmit and receive data
LCR[5] = logic 1 and LCR[4] = logic 1: parity bit is forced to a logic 0 for
the transmit and receive data
4
LCR[4]
Parity type select.
logic 0 = odd parity is generated (if LCR[3] = 1)
logic 1 = even parity is generated (if LCR[3] = 1)
3
LCR[3]
Parity enable.
logic 0 = no parity (normal default condition)
logic 1 = a parity bit is generated during transmission and the receiver
checks for received parity
2
LCR[2]
Number of stop bits. Species the number of stop bits.
0 = 1 stop bit (word length = 5, 6, 7, 8)
1 = 1.5 stop bits (word length = 5)
1 = 2 stop bits (word length = 6, 7, 8)
1:0
LCR[1:0]
Word length bits 1, 0. These two bits specify the word length to be
transmitted or received.
00 — 5 bits
01 — 6 bits
10 — 7 bits
11 — 8 bits
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