參數(shù)資料
型號: SC16C654BIBM,128
廠商: NXP Semiconductors
文件頁數(shù): 32/58頁
文件大小: 0K
描述: IC QUAD UART 64BYTE 64LQFP
標(biāo)準(zhǔn)包裝: 2,000
特點: 故障啟動位檢測
通道數(shù): 4,QUART
FIFO's: 64 字節(jié)
電源電壓: 2.5V,3.3V,5V
帶自動流量控制功能:
帶IrDA 編碼器/解碼器:
帶故障啟動位檢測功能:
帶調(diào)制解調(diào)器控制功能:
帶CMOS:
安裝類型: 表面貼裝
封裝/外殼: 64-LQFP
供應(yīng)商設(shè)備封裝: 64-LQFP(7x7)
包裝: 帶卷 (TR)
其它名稱: 935279068128
SC16C654BIBM-F
SC16C654BIBM-F-ND
38
7674F–AVR–09/09
ATmega164P/324P/644P
When applying an external clock, it is required to avoid sudden changes in the applied clock fre-
quency to ensure stable operation of the MCU. A variation in frequency of more than 2% from
one clock cycle to the next can lead to unpredictable behavior. If changes of more than 2% is
required, ensure that the MCU is kept in Reset during the changes.
Note that the System Clock Prescaler can be used to implement run-time changes of the internal
clock frequency while still ensuring stable operation. Refer to “System Clock Prescaler” on page
38 for details.
7.9
Timer/Counter Oscillator
ATmega164P/324P/644P uses the same type of crystal oscillator for Low-frequency Crystal
Oscillator and Timer/Counter Oscillator. See “Low Frequency Crystal Oscillator” on page 34 for
details on the oscillator and crystal requirements.
The device can operate its Timer/Counter2 from an external 32.768 kHz watch crystal or a exter-
nal clock source. See “Clock Source Connections” on page 31 for details.
Applying an external clock source to TOSC1 can be done if EXTCLK in the ASSR Register is
description on selecting external clock as input instead of a 32.768 kHz watch crystal.
7.10
Clock Output Buffer
The device can output the system clock on the CLKO pin. To enable the output, the CKOUT
Fuse has to be programmed. This mode is suitable when the chip clock is used to drive other cir-
cuits on the system. The clock also will be output during reset, and the normal operation of I/O
pin will be overridden when the fuse is programmed. Any clock source, including the internal RC
Oscillator, can be selected when the clock is output on CLKO. If the System Clock Prescaler is
used, it is the divided system clock that is output.
7.11
System Clock Prescaler
The ATmega164P/324P/644P has a system clock prescaler, and the system clock can be
divided by setting the “CLKPR – Clock Prescale Register” on page 40. This feature can be used
to decrease the system clock frequency and the power consumption when the requirement for
processing power is low. This can be used with all clock source options, and it will affect the
clock frequency of the CPU and all synchronous peripherals. clk
I/O, clkADC, clkCPU, and clkFLASH
are divided by a factor as shown in Table 7-16 on page 40.
Table 7-15.
Start-up Times for the External Clock Selection
Power Conditions
Start-up Time from
Power-down and Power-save
Additional Delay from
Reset (VCC = 5.0V)
SUT1..0
BOD enabled
6 CK
14CK
00
Fast rising power
6 CK
14CK + 4.1 ms
01
Slowly rising power
6 CK
14CK + 65 ms
10
Reserved
11
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