參數(shù)資料
型號(hào): SC16C550BIBS,151
廠商: NXP Semiconductors
文件頁數(shù): 8/48頁
文件大?。?/td> 0K
描述: IC UART SINGLE W/FIFO 32-HVQFN
標(biāo)準(zhǔn)包裝: 490
特點(diǎn): 可編程
通道數(shù): 1,UART
FIFO's: 16 字節(jié)
電源電壓: 2.5V,3.3V,5V
帶自動(dòng)流量控制功能:
帶故障啟動(dòng)位檢測(cè)功能:
帶調(diào)制解調(diào)器控制功能:
帶CMOS:
安裝類型: 表面貼裝
封裝/外殼: 32-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 32-HVQFN(5x5)
包裝: 托盤
其它名稱: 568-3263
935279497151
SC16C550BIBS-S
SC16C550B_5
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 05 — 1 October 2008
16 of 48
NXP Semiconductors
SC16C550B
5 V, 3.3 V and 2.5 V UART with 16-byte FIFOs
6.7 Loopback mode
The internal loopback capability allows on-board diagnostics. In the loopback mode, the
normal modem interface pins are disconnected and recongured for loopback internally.
MCR[3:0] register bits are used for controlling loopback diagnostic testing. In the loopback
mode, OUT1 (bit 2) and OUT2 (bit 3) in the MCR register control the modem RI and DCD
inputs, respectively. MCR signals DTR and RTS (bits 0:1) are used to control the modem
CTS and DSR inputs, respectively. The transmitter output (TX) and the receiver input (RX)
are disconnected from their associated interface pins, and instead are connected together
internally (see Figure 11). The inputs CTS, DSR, DCD, and RI are disconnected from
their normal modem control input pins, and instead are connected internally to DTR, RTS,
OUT1 and OUT2. Loopback test data is entered into the transmit holding register via the
user data bus interface, D0 to D7. The transmit UART serializes the data and passes the
serial data to the receive UART via the internal loopback connection. The receive UART
converts the serial data back into parallel data that is then made available at the user data
interface D0 to D7. The user optionally compares the received data to the initial
transmitted data for verifying error-free operation of the UART TX/RX circuits.
In this mode, the receiver and transmitter interrupts are fully operational. The Modem
Control Interrupts are also operational. However, the interrupts can only be read using the
lower four bits of the Modem Status Register (MSR[3:0]) instead of the four Modem Status
Register bits 7:4. The interrupts are still controlled by the IER.
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