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參數(shù)資料
| 型號(hào)： | SBDIP |
| 廠商： | Intersil Corporation |
| 英文描述： | High-Reliability CMOS 8-Bit Microprocessor |
| 中文描述： | 高可靠性的CMOS 8位微處理器 |
| 文件頁數(shù)： | 4/8頁 |
| 文件大小： | 44K |
| 代理商： | SBDIP |
3-33
Input Low Voltage, V
IL
0.5, 4.5
-
5
-
1.5
-
1.5
V
Input High Voltage, V
IH
0.5, 4.5
-
5
3.5
-
3.5
-
V
Input Leakage Current, I
IN
Any
Input
0, 5
5
-
±
1
-
±
5
μ
A
Three-State Output Leakage
Current, I
OUT
0, 5
0, 5
5
-
±
1
-
±
5
μ
A
NOTE:
2. 5V level characteristics apply to Part No. CDP1802AC/3, and 5V and 10V level characteristics apply to part No. CDP1802A/3.
Timing Specifications
As a Function of T (T = 1/fCLOCK), C
L
= 50 pF
PARAMETER
V
DD
(V)
LIMITS
(NOTE 3)
-55
o
C, +25
o
C
+125
o
C
UNITS
High-Order Memory-Address Byte Setup to TPA
Time, t
SU
5
2T-450
2T-580
ns
High-Order Memory-Address Byte Hold After TPA Time, t
H
5
T/2 +0
T/2 +0
ns
Low-Order Memory-Address Byte Hold After WR Time, t
H
5
T-30
T-40
ns
CPU Data to Bus Hold After WR Time, t
H
5
T-170
T-250
ns
Required Memory Access Time Address to Data, t
ACC
5
5T-300
5T-400
ns
NOTE:
3. These limits are not directly tested.
Implicit Specifications
(Note 4) T
A
= -55
o
C to +25
o
C
PARAMETER
SYMBOL
V
DD
(V)
TYPICAL
VALUES
UNITS
Typical Total Power Dissipation
Idle “00” at M(0000), C
L
= 50pF
f = 2MHz
-
5
4
mW
Effective Input Capacitance any Input
-
C
IN
-
5
pF
Effective Three-State Terminal Capacitance Data Bus
-
-
7.5
pF
Minimum Data Retention Voltage
-
V
DR
-
2.4
V
Data Retention Current
-
I
DR
2.4
10
μ
A
NOTE:
4. These specifications are not tested. Typical values are provided for guidance only.
Static Electrical Specifications
All Limits are 100% Tested
(Continued)
PARAMETER
CONDITIONS
-55
o
C, +25
o
C
+125
o
C
UNITS
V
OUT
(V)
V
IN,
(V)
V
CC,
V
DD
(V)
MIN
MAX
MIN
MAX
CDP1802AC/3
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