參數(shù)資料
型號: SB80C188EC13
廠商: INTEL CORP
元件分類: 微控制器/微處理器
英文描述: 16-BIT, 13 MHz, MICROPROCESSOR, PQFP100
封裝: SHRINK, QFP-100
文件頁數(shù): 30/57頁
文件大?。?/td> 1573K
代理商: SB80C188EC13
80C186EC188EC 80L186EC188EC
Relative Timings (80C186EC-252013 80L186EC-1613)
NOTES
1 Assumes equal loading on both pins
2 Can be extended using wait states
3 Interrupt resolution time is the delay between an unmasked interrupt request going active and the interrupt output of the
8259A module going active This is not directly measureable by the user For interrupt pin INT7 the delay from an active
signal to an active input to the CPU would actually be twice the TIRES value since the signal must pass through two 8259A
modules
4 See INTA Cycle Waveforms for definition
5 To guarantee interrupt is not spurious
Serial Port Mode 0 Timings (80C186EC-252013 80L186EC-1613)
Symbol
Parameter
Min
Max
Unit
Notes
RELATIVE TIMINGS
TXLXL
TXD Clock Period
T (n a 1)
ns
1 2
TXLXH
TXD Clock Low to Clock High (N l 1)
2T b 35
2T a 35
ns
1
TXLXH
TXD Clock Low to Clock High (N e 1)
T b 35
T a 35
ns
1
TXHXL
TXD Clock High to Clock Low (N l 1)
(n b 1) T b 35
(n b 1) T a 35
ns
1 2
TXHXL
TXD Clock High to Clock Low (N e 1)
T b 35
T a 35
ns
1
TQVXH
RXD Output Data Setup to TXD
(n b 1)T b 35
ns
1 2
Clock High (N l 1)
TQVXH
RXD Output Data Setup to TXD
T b 35
ns
1
Clock High (N e 1)
TXHQX
RXD Output Data Hold after TXD
2T b 35
ns
1
Clock High (N l 1)
TXHQX
RXD Output Data Hold after TXD
T b 35
ns
1
Clock High (N e 1)
TXHQZ
RXD Output Data Float after Last
T a 20
ns
1
TXD Clock High
TDVXH
RXD Input Data Setup to TXD
T a 20
ns
1
Clock High
TXHDX
RXD Input Data Setup after TXD
0
ns
1
Clock High
NOTES
1 See Figure 13 for Waveforms
2 n is the value in the BxCMP register ignoring the ICLK bit
36
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參數(shù)描述
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