參數(shù)資料
型號(hào): SB80C188EC13
廠商: INTEL CORP
元件分類: 微控制器/微處理器
英文描述: 16-BIT, 13 MHz, MICROPROCESSOR, PQFP100
封裝: SHRINK, QFP-100
文件頁數(shù): 27/57頁
文件大?。?/td> 1573K
代理商: SB80C188EC13
80C186EC188EC 80L186EC188EC
AC Characteristics80L186EC13
Symbol
Parameter
Min
Max
Unit
Notes
INPUT CLOCK
13 MHz
TF
CLKIN Frequency
0
26
MHz
1
TC
CLKIN Period
385
%
ns
1
TCH
CLKIN High Time
15
%
ns
1 2
TCL
CLKIN Low Time
15
%
ns
1 2
TCR
CLKIN Rise Time
1
10
ns
1 3
TCF
CLKIN Fall Time
1
10
ns
1 3
OUTPUT CLOCK
TCD
CLKIN to CLKOUT Delay
0
20
ns
1 4
T
CLKOUT Period
2
TC
ns
1
TPH
CLKOUT High Time
(T2) b 5
(T2) a 5ns
1
TPL
CLKOUT Low Time
(T2) b 5
(T2) a 5ns
1
TPR
CLKOUT Rise Time
1
10
ns
1 5
TPF
CLKOUT Fall Time
1
10
ns
1 5
OUTPUT DELAYS
TCHOV1
S20 DTR BHE LOCK
3
28
ns
1 4 6 7
TCHOV2
LCS UCS DEN A1916 RD WR NCS
3
32
ns
1 4 6 8
WDTOUT ALE
TCHOV3
GCS70
3
34
ns
1 4 6
TCLOV1
LOCK RESOUT HLDA T0OUT T1OUT
3
28
ns
1 4 6
TCLOV2
RD WR AD150 (AD70 A158) BHE
3
32
ns
1 4 6
(RFSH) NCS INTA DEN
TCLOV3
GSC70 LCS UCS
3
34
ns
1 4 6
TCLOV4
S20 A1916
3
37
ns
1 4 6
TCHOF
RD WR BHE (RFSH) DTR LOCK
0
30
ns
1
S20 A1916
TCLOF
DEN AD150 (AD70 A158)
0
35
ns
1
INPUT REQUIREMENTS
TCHIS
TEST NMI T1IN T0IN READY
20
ns
1 9
CTS10 BCLK10 P34 P35
TCHIH
TEST NMI T1IN T0IN READY
3
ns
1 9
CTS10 BCLK10 P34 P35
TCLIS
AD150 (AD70) READY
20
ns
1 10
TCLIH
AD150 (AD70) READY
3
ns
1 10
TCLIS
HOLD RESIN PEREQ ERROR DRQ30
20
ns
1 9
TCLIH
HOLD RESIN REREQ ERROR DRQ30
3
ns
1 9
NOTES
1 See AC Timing Waveforms for waveforms and definition
2 Measure at VIH for high time VIL for low time
3 Only required to guarantee ICC Maximum limits are bounded by TC TCH and TCL
4 Specified for a 50 pF load see Figure 14 for capacitive derating information
5 Specified for a 50 pF load see Figure 15 for rise and fall times outside 50 pF
33
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