參數(shù)資料
型號(hào)： SB80C188EC-25
廠商： INTEL CORP
元件分類： 微控制器/微處理器
英文描述： 16-BIT, 25 MHz, MICROPROCESSOR, PQFP100
封裝： SHRINK, QFP-100
文件頁數(shù)： 6/57頁
文件大?。?/td> 1573K
代理商： SB80C188EC-25
80C186EC188EC 80L186EC188EC
Table 2 Pin Descriptions
(Continued)
Pin Name
Pin
Input
Output
Pin Description
Type
States
P31TXI1
O
H(X)H(Q)
Transmit Interrupt
output goes active to indicate that
serial channel 1 has completed a transfer TXI1 is
R(0)
multiplexed with an output only Port function
I(Q)
P(X)
P30RXI1
O
H(X)H(Q)
Receive Interrupt
output goes active to indicate that
serial channel 1 has completed a reception RXI1 is
R(0)
multiplexed with an output only port function
I(Q)
P(X)
WDTOUT
O
H(Q)
WatchDog Timer OUTput
is driven low for four clock
cycles when the watchdog timer reaches zero WDTOUT
R(1)
may be ANDed with the power-on reset signal to reset the
I(Q)
processor when the watchdog timer is not properly reset
P(X)
P27CTS1
IO
A(L)
H(X)
Clear-To-Send
input is used to prevent the transmission
of serial data on the TXD signal pin CTS1 and CTS0 are
P23CTS0
R(Z)
multiplexed with an IO Port function
I(X)
P(X)
P26BCLK1
IO
A(L)
H(X)
Baud CLocK
input can be used as an alternate clock
source for each of the integrated serial channels The
P22BCLK0
A(E)
R(Z)
BCLK inputs are multiplexed with IO Port functions The
I(X)
BCLK input frequency cannot exceed
the operating
P(X)
frequency of the processor
P25TXD1
IO
A(L)
H(Q)
Transmit Data
output provides serial data information
The TXD outputs are multiplexed with IO Port functions
P21TXD0
R(Z)
During synchronous serial communications TXD will
I(X)I(Q)
function as a clock output
P(X)
P24RXD1
IO
A(L)
H(X)H(Q)
Receive Data
input accepts serial data information The
RXD pins are multiplexed with IO Port functions During
P20RXD0
R(Z)
synchronous serial communications RXD is bi-directional
I(X)I(Q)
and will become an output for transmission of data (TXD
P(X)
becomes the clock)
DRQ30
I
A(L)
DMA ReQuest
input pins are used to request a DMA
transfer The timing of the request is dependent on the
programmed synchronization mode
NOTES
1 READY is A(E) for the rising edge of CLKOUT S(E) for the falling edge of CLKOUT
2 Pin names in parentheses apply to the 80C188EC80L188EC
14
相關(guān)PDF資料
PDF描述
S80C188EC25 16-BIT, 25 MHz, MICROPROCESSOR, PQFP100
SB80C188EC13 16-BIT, 13 MHz, MICROPROCESSOR, PQFP100
SB80C188EC20 16-BIT, 20 MHz, MICROPROCESSOR, PQFP100
SB80L186EC13 16-BIT, 13 MHz, MICROPROCESSOR, PQFP100
SB80L186EB8 16-BIT, 8 MHz, MICROPROCESSOR, PQFP80
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