參數資料
型號： SB80C188EC-25
廠商： INTEL CORP
元件分類： 微控制器/微處理器
英文描述： 16-BIT, 25 MHz, MICROPROCESSOR, PQFP100
封裝： SHRINK, QFP-100
文件頁數： 22/57頁
文件大?。?/td> 1573K
代理商： SB80C188EC-25
80C186EC188EC 80L186EC188EC
ICC versus Frequency and Voltage
The ICC consumed by the processor is composed of
two components
1 IPD The quiescent current that represents inter-
nal device leakage Measured with all inputs at
either VCC or ground and no clock applied
2 ICCS The switching current used to charge and
discharge internal parasitic capacitance when
changing logic levels ICCS is related to both the
frequency of operation and the device supply
voltage (VCC) ICCS is given by the formula
Power e V
I e V2
CDEV
f
ICCS e V
CDEV
f
Where
V e Supply Voltage (VCC)
CDEV e Device Capacitance
f e Operating Frequency
Measuring CPD on a device like the 80C186EC
would be difficult Instead CPD is calculated using
the above formula with ICC values measured at
known VCC and frequency Using the CPD value the
user can calculate ICC at any voltage and frequency
within the specified operating range
Example
Calculate typical ICC at 14 MHz 52V VCC
ICC e IPD a ICCS
e
01 mA a 52V
077
14 MHz
e
562 mA
PDTMR Pin Delay Calculation
The PDTMR pin provides a delay between the as-
sertion of NMI and the enabling of the internal
clocks when exiting Powerdown Mode A delay is
required only when using the on chip oscillator to
allow the crystal or resonator circuit to stabilize
NOTE
The PDTMR pin function does not apply when
RESIN is asserted (ie a device reset while in Pow-
erdown is similar to a cold reset and RESIN must
remain active until after the oscillator has stabilized
To calculate the value of capacitor to use to provide
a desired delay use the equation
440 c t e CPD (5V 25 C)
Where
t e desired delay in seconds
CPD e capacitive load on PDTMR in microfarads
Example
For a delay of 300 ms a capacitor value of
CPD e 440 c (300 c 10b6 e 0132 mF is required
Round up to a standard (available) capacitor value
NOTE
The above equation applies to delay time longer
than 10 ms and will compute the TYPICAL capaci-
tance needed to achieve the desired delay A delay
variance of a50% to b25% can occur due to
temperature
voltage
and device process ex-
tremes In general higher VCC andor lower tem-
peratures will decrease delay time while lower VCC
andor higher temperature will increase delay time
Parameter
Typical
Max
Units
Notes
CPD
077
137
mAV MHz
1 2
CPD (Idle Mode)
055
096
mAV MHz
1 2
NOTES
1 Maximum CPD is measured at b40 C with all outputs loaded as specified in the AC test conditions and the device in reset
(or Idle Mode) Due to tester limitations CLKOUT and OSCOUT also have 50 pF loads that increase ICC by V C F
2 Typical CPD is calculated at 25 C assuming no loads on CLKOUT or OSCOUT and the device in reset (or Idle Mode)
29
相關PDF資料
PDF描述
S80C188EC25 16-BIT, 25 MHz, MICROPROCESSOR, PQFP100
SB80C188EC13 16-BIT, 13 MHz, MICROPROCESSOR, PQFP100
SB80C188EC20 16-BIT, 20 MHz, MICROPROCESSOR, PQFP100
SB80L186EC13 16-BIT, 13 MHz, MICROPROCESSOR, PQFP100
SB80L186EB8 16-BIT, 8 MHz, MICROPROCESSOR, PQFP80
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