參數(shù)資料
型號: SAK-XC2230L-12F80L
廠商: INFINEON TECHNOLOGIES AG
元件分類: 微控制器/微處理器
英文描述: 32-BIT, FLASH, 80 MHz, RISC MICROCONTROLLER, PQFP64
封裝: 0.50 MM PITCH, GREEN, PLASTIC, LQFP-64
文件頁數(shù): 66/113頁
文件大?。?/td> 3160K
代理商: SAK-XC2230L-12F80L
XC2230L, XC2234L
XC2000 Family / Econo Line
Functional Description
PRELIMINARY
Data Sheet
52
V1.0, 2010-12
3.17
Parallel Ports
The XC223[04]L provides up to 48 I/O lines which are organized into 3 input/output ports
and 1 input port. All port lines are bit-addressable, and all input/output lines can be
individually (bit-wise) configured via port control registers. This configuration selects the
direction (input/output), push/pull or open-drain operation, activation of pull devices, and
edge characteristics (shape) and driver characteristics (output current) of the port
drivers. The I/O ports are true bidirectional ports which are switched to high impedance
state when configured as inputs. During the internal reset, all port pins are configured as
inputs without pull devices active.
All port lines have alternate input or output functions associated with them. These
alternate functions can be programmed to be assigned to various port pins to support the
best utilization for a given application. For this reason, certain functions appear several
times in Table 10.
All port lines that are not used for alternate functions may be used as general purpose
I/O lines.
Table 10
Summary of the XC223[04]L’s Ports
Group
Width
I/O
Connected Modules
P2
14
I/O
Analog inputs, ADC, CAN, CC2, CCU6, DAP/JTAG,
GPT12E, SCU, USIC
P5
14
I
Analog inputs, CCU6, JTAG, GPT12E, CC2
P6
4
I/O
Analog inputs, ADC, CCU6, JTAG, GPT12E, USIC
P10
16
I/O
CAN, CCU6, GPT12E, DAP/JTAG, SPD, USIC
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