參數(shù)資料
型號: SAK-TC1762-128F80HL
廠商: INFINEON TECHNOLOGIES AG
元件分類: 微控制器/微處理器
英文描述: 32-BIT, FLASH, 80 MHz, MICROCONTROLLER, PQFP176
封裝: PLASTIC, LQFP-176
文件頁數(shù): 58/114頁
文件大?。?/td> 852K
代理商: SAK-TC1762-128F80HL
TC1762
Functional Description
Preliminary
Data Sheet
44
V1.0, 2008-04
3.12.1
Functionality of GPTA0
The General Purpose Timer Array GPTA0 provides a set of hardware modules required
for high-speed digital signal processing:
Filter and Prescaler Cells (FPC) support input noise filtering and prescaler operation.
Phase Discrimination Logic units (PDL) decode the direction information output by a
rotation tracking system.
Duty
Cycle
Measurement
Cells
(DCM)
provide
pulse-width
measurement
capabilities.
A Digital Phase Locked Loop unit (PLL) generates a programmable number of GPTA
module clock ticks during an input signal’s period.
Global Timer units (GT) driven by various clock sources are implemented to operate
as a time base for the associated Global Timer Cells.
Global Timer Cells (GTC) can be programmed to capture the contents of a Global
Timer on an external or internal event. A GTC may also be used to control an external
port pin depending on the result of an internal compare operation. GTCs can be
logically concatenated to provide a common external port pin with a complex signal
waveform.
Local Timer Cells (LTC) operating in Timer, Capture, or Compare Mode may also be
logically tied together to drive a common external port pin with a complex signal
waveform. LTCs — enabled in Timer Mode or Capture Mode — can be clocked or
triggered by various external or internal events.
Input lines can be shared by an LTC and a GTC to trigger their programmed operation
simultaneously.
The following list summarizes the specific features of the GPTA unit.
Clock Generation Unit
Filter and Prescaler Cell (FPC)
– Six independent units
– Three basic operating modes:
Prescaler, Delayed Debounce Filter, Immediate Debounce Filter
– Selectable input sources:
Port lines, GPTA module clock, FPC output of preceding FPC cell
– Selectable input clocks:
GPTA module clock, prescaled GPTA module clock, DCM clock, compensated or
uncompensated PLL clock
f
GPTA/2 maximum input signal frequency in Filter Modes
Phase Discriminator Logic (PDL)
– Two independent units
– Two operating modes (2- and 3-sensor signals)
f
GPTA/4 maximum input signal frequency in 2-sensor Mode, fGPTA/6 maximum input
signal frequency in 3-sensor Mode
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