參數(shù)資料
型號: SAK-TC1762-128F80HL
廠商: INFINEON TECHNOLOGIES AG
元件分類: 微控制器/微處理器
英文描述: 32-BIT, FLASH, 80 MHz, MICROCONTROLLER, PQFP176
封裝: PLASTIC, LQFP-176
文件頁數(shù): 42/114頁
文件大小: 852K
代理商: SAK-TC1762-128F80HL
TC1762
Functional Description
Preliminary
Data Sheet
29
V1.0, 2008-04
3.5
DMA Controller and Memory Checker
The DMA Controller of the TC1762 transfers data from data source locations to data
destination locations without intervention of the CPU or other on-chip devices. One data
move operation is controlled by one DMA channel. Eight DMA channels are provided in
one DMA Sub-Block. The Bus Switch provides the connection of the DMA Sub-Block to
the two FPI Bus interfaces and an MLI bus interface. In the TC1762, the FPI Bus
interfaces are connected to the System Peripheral Bus and the DMA Bus. The third
specific bus interface provides a connection to the Micro Link Interface module (MLI0 in
the TC1762) and other DMA-related devices (Memory Checker module in the TC1762).
Clock control, address decoding, DMA request wiring, and DMA interrupt service request
control are implementation-specific and managed outside the DMA controller kernel.
Figure 3-1 shows the implementation details and interconnections of the DMA module.
Figure 3-1
DMA Controller Block Diagram
Features
8 independent DMA channels
Interrupt
Request
Nodes
MCB06149
Clock
Control
f
DMA
SR[15:0]
DMA Controller
Arbiter/
Switch
Control
Bus
Switch
FP
IB
u
s
In
te
rf
a
c
e
0
FP
IB
u
s
In
te
rf
a
c
e
1
ML
I
In
te
rf
a
c
e
Memory
Checker
MLI0
System
Periphera
Bus
DMA Bus
DMA
Requests
of
On-chip
Periph.
Units
Address
Decoder
DMA Interrupt Control
CH0n_OUT
DMA
Channels
00-07
DMA Sub-Block 0
Request
Selection/
Arbitration
Transaction
Control Unit
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