參數(shù)資料
型號: SAK-TC1762-128F66HL
廠商: INFINEON TECHNOLOGIES AG
元件分類: 微控制器/微處理器
英文描述: 32-BIT, FLASH, 66 MHz, MICROCONTROLLER, PQFP176
封裝: PLASTIC, LQFP-176
文件頁數(shù): 53/114頁
文件大?。?/td> 852K
代理商: SAK-TC1762-128F66HL
TC1762
Functional Description
Preliminary
Data Sheet
39
V1.0, 2008-04
3.10
MultiCAN Controller (CAN)
Figure 3-6 shows a global view of the MultiCAN module with its functional blocks and
interfaces.
Figure 3-6
Block Diagram of MultiCAN Module
The MultiCAN module contains two independently-operating CAN nodes with Full-CAN
functionality that are able to exchange Data and Remote Frames via a gateway function.
Transmission and reception of CAN frames is handled in accordance with CAN
specification V2.0 B (active). Each CAN node can receive and transmit standard frames
with 11-bit identifiers as well as extended frames with 29-bit identifiers.
Both CAN nodes share a common set of message objects. Each message object can be
individually allocated to one of the CAN nodes. Besides serving as a storage container
for incoming and outgoing frames, message objects can be combined to build gateways
between the CAN nodes or to setup a FIFO buffer.
The message objects are organized in double-chained linked lists, where each CAN
node has its own list of message objects. A CAN node stores frames only into message
objects that are allocated to the message object list of the CAN node, and it transmits
only messages belonging to this message object list. A powerful, command-driven list
controller performs all message object list operations.
The bit timings for the CAN nodes are derived from the module timer clock (
f
CAN), and
are programmable up to a data rate of 1 Mbit/s. External bus transceivers are connected
to a CAN node via a pair of receive and transmit pins.
MultiCAN Module Kernel
MCA06281
Interrupt
Control
f
CAN
Port 3
Control
CAN Control
Message
Object
Buffer
64
Objects
TXDC0
RXDC0
TXDC1
RXDC1
Linked
List
Control
P3.15 /
TXDCAN1
P3.14 /
RXDCAN1
P3.13 /
TXDCAN0
P3.12 /
RXDCAN0
f
CLC
Clock
Control
Address
Decoder
DMA
INT_O
[1:0]
INT_O15
INT_O
[5:2]
CAN
Node 0
CAN
Node 1
A2
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