參數(shù)資料
型號: SAK-TC1762-128F66HL
廠商: INFINEON TECHNOLOGIES AG
元件分類: 微控制器/微處理器
英文描述: 32-BIT, FLASH, 66 MHz, MICROCONTROLLER, PQFP176
封裝: PLASTIC, LQFP-176
文件頁數(shù): 110/114頁
文件大?。?/td> 852K
代理商: SAK-TC1762-128F66HL
TC1762
Electrical Parameters
Preliminary
Data Sheet
91
V1.0, 2008-04
4.3.3
Power Sequencing
There is a restriction for the power sequencing of the 3.3 V domain as shown in
Figure 4-9. It must always be higher than 1.5 V domain - 0.5 V. The gray area shows the
valid range for V
3.3V relative to an exemplary V1.5V ramp. VDDP, VDDOSC3, VDDM, VDDMF,
V
DDFL3 belong to the 3.3 V domain. The VDDM and VDDMF subdomains are connected with
antiparallel ESD protection diodes. There are no other such connections between the
subdomains. V
DD , VDDOSC and VDDAF belong to the 1.5 V domain.
Figure 4-9
V
DDP / VDD Power Up Sequence
All ground pins V
SS must be externally connected to one single star point in the system.
The difference voltage between the ground pins must not exceed 200 mV.
The PORST signal must be activated at latest before any power supply voltage falls
below the levels shown on the figure below. In this case, only the memory row of a Flash
memory that was the target of the write at the moment of the power loss will contain
unreliable content. Additionally, the PORST signal should be activated as soon as
possible. The sooner the PORST signal is activated, the less time the system operates
outside of the normal operating power supply range.
PowerSeq
1.5V
3.3V
V
1.5
V
3.3
V
3.3 > V1.5 - 0.5V
Time
Power Supply Voltage
V
al
id
ar
e
a
fo
r
V
3.
3
V
al
id
a
re
a
fo
r
V
3.3
Time
V
DD P
(3.3V)
PORST
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