- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄374698 > SAK-C164SL-8RM (INFINEON TECHNOLOGIES AG) 16-Bit Single-Chip Microcontroller PDF資料下載
參數(shù)資料
| 型號(hào)： | SAK-C164SL-8RM |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 英文描述： | 16-Bit Single-Chip Microcontroller |
| 中文描述： | 16位單片機(jī) |
| 文件頁(yè)數(shù)： | 54/79頁(yè) |
| 文件大?。?/td> | 1314K |
| 代理商： | SAK-C164SL-8RM |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)當(dāng)前第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)
C164CI/SI
C164CL/SL
Data Sheet
50
V2.0, 2001-05
AC Characteristics
Definition of Internal Timing
The internal operation of the C164CI is controlled by the internal CPU clock
f
CPU
. Both
edges of the CPU clock can trigger internal (e.g. pipeline) or external (e.g. bus cycles)
operations.
The specification of the external timing (AC Characteristics) therefore depends on the
time between two consecutive edges of the CPU clock, called
“
TCL
”
(see
Figure 11
).
Figure 11
Generation Mechanisms for the CPU Clock
The CPU clock signal
f
CPU
can be generated from the oscillator clock signal
f
OSC
via
different mechanisms. The duration of TCLs and their variation (and also the derived
external timing) depends on the used mechanism to generate
f
CPU
. This influence must
be regarded when calculating the timings for the C164CI.
Note: The example for PLL operation shown in
Figure 11
refers to a PLL factor of 4.
The used mechanism to generate the basic CPU clock is selected by bitfield CLKCFG
in register RP0H.7-5.
Upon a long hardware reset register RP0H is loaded with the logic levels present on the
upper half of PORT0 (P0H), i.e. bitfield CLKCFG represents the logic levels on pins
MCT04338
f
OSC
f
CPU
Phase Locked Loop Operation
TCL
f
OSC
f
CPU
Direct Clock Drive
f
OSC
f
CPU
Prescaler Operation
TCL
TCL
TCL
TCL
TCL
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SAK-C164SM-4R25F | 16-Bit Single-Chip Microcontrol ler |
| SAK-C164CM-4EF | 16-Bit Single-Chip Microcontrol ler |
| SAF-C164CM-4EF | 16-Bit Single-Chip Microcontrol ler |
| SAK-C164CM-4R25F | 16-Bit Single-Chip Microcontrol ler |
| SAF-C164CM-4R25F | 16-Bit Single-Chip Microcontrol ler |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SAK-C164SM-4R25F | 制造商:INFINEON 制造商全稱(chēng):Infineon Technologies AG 功能描述:16-Bit Single-Chip Microcontrol ler |
| SAK-C164SM-4RF | 制造商:INFINEON 制造商全稱(chēng):Infineon Technologies AG 功能描述:16-Bit Single-Chip Microcontrol ler |
| SAK-C164SV-2R25F | 制造商:INFINEON 制造商全稱(chēng):Infineon Technologies AG 功能描述:16-Bit Single-Chip Microcontroller |
| SAK-C164SV-2RF | 制造商:STMicroelectronics 功能描述:TQFP-64 16BIT ROM MCU - Trays |
| SAK-C167CR-16R33M | 制造商:INFINEON 制造商全稱(chēng):Infineon Technologies AG 功能描述:16-Bit Single-Chip Microcontroller |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。