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C161U
Central Processor Unit
Data Sheet
90
2001-04-19
The PEC transfer counter allows to service a specified number of requests by the
respective PEC channel, and then (when COUNT reaches 00
H
) activate the interrupt
service routine, which is associated with the priority level. After each PEC transfer the
COUNT field is decremented and the request flag is cleared to indicate that the request
has been serviced.
Continuous transfers
are selected by the value FF
H
in bit field COUNT. In this case
COUNT is not modified and the respective PEC channel services any request until it is
disabled again.
When COUNT is decremented from 01
H
to 00
H
after a transfer, the request flag is not
cleared, which generates another request from the same source. When COUNT already
contains the value 00
H
, the respective PEC channel remains idle and the associated
interrupt service routine is activated instead. This allows to choose, if a level 15 or 14
request is to be serviced by the PEC or by the interrupt service routine.
Note:
PEC transfers are only executed, if their priority level is higher than the CPU level,
ie. only PEC channels 7...4 are processed, while the CPU executes on level 14.
All interrupt request sources that are enabled and programmed for PEC service
should use different channels. Otherwise only one transfer will be performed for
all simultaneous requests. When COUNT is decremented to 00
H
, and the CPU is
to be interrupted, an incorrect interrupt vector will be generated.
Channel Link control bit CL
controls the channel link mode. In this mode PEC
channels work by pair (channels 0 and 1, 2 and 3, 4 and 5, 6 and 7). The channel link
mode is enabled for one pair when the CL bit is set in any of the 2 PECCx registers. In
this case, the 2 channels handle PEC requests alternative to each other. The whole data
transfer is divided into several block transfers where each block is controlled by a PEC
channel. When a block transfer is completed, a channel link interrupt is generated and
the request processing is switched to the other PEC channel of the pair. This mechanism
allows to set up shadow and multiple buffers for PEC transfers by changing pointers and
count values of one channel when the other channel is active.
The very first transfer is always initiated with the even channel (called channel A, that is
channel 0, 2, 4 or 6). When the associated count field reaches 0 (COUNT or COUNT2
depending on the selected mode), the request service is transfered to the odd channel
(channel B, that is channel 1, 3, 5 or 7). If the CL bit of the "linked" channel is set and the
count field is different from 0, the next PEC requests will be serviced by this channel.
The channel link interrupts share one common interrupt node (Trap number 4C
H
- vector
location 00’0130
H
). This node is controlled by the Channel Link Interrupt Sub-Node
Control (CLISNC) register. It raises an interrupt request in case of one or more channel
link request flag and the respective enable control bit is set in CLISNC register. These
flags signal a PEC condition of the PEC linked channels which requires an action from
the CPU. The following conditions are possible:
1. In single transfer mode, a COUNT value change from 01
H
to 00
H
in a linked PEC
channel and the CL flag is set in the respective PEC control register,