參數(shù)資料
型號(hào): SAF-XC2224L-20F66V
廠商: INFINEON TECHNOLOGIES AG
元件分類: 微控制器/微處理器
英文描述: 32-BIT, FLASH, 66 MHz, RISC MICROCONTROLLER, PQCC48
封裝: 0.50 MM PITCH, GREEN, PLASTIC, VQFN-48
文件頁數(shù): 95/112頁
文件大?。?/td> 3122K
代理商: SAF-XC2224L-20F66V
XC2220L, XC2224L
XC2000 Family / Econo Line
Electrical Parameters
PRELIMINARY
Data Sheet
79
V1.0, 2010-12
Access to the XC222[04]L Flash modules is controlled by the IMB. Built-in prefetch
mechanisms optimize the performance for sequential access.
Flash access waitstates only affect non-sequential access. Due to prefetch
mechanisms, the performance for sequential access (depending on the software
structure) is only partially influenced by waitstates.
Number of erase cycles
N
ER SR
15000 cycle
s
t
RET≥ 5 years;
Valid for up to
64 user
selected
sectors (data
storage)
1000
cycle
s
t
RET≥ 20 years
1) All Flash module(s) can be erased/programmed while code is executed and/or data is read from only one Flash
module or from PSRAM. The Flash module that delivers code/data can, of course, not be erased/programmed.
2) Flash module 1 can be erased/programmed while code is executed and/or data is read from Flash module 0.
3) Value of IMB_IMBCTRL.WSFLASH.
4) Programming and erase times depend on the internal Flash clock source. The control state machine needs a
few system clock cycles. This increases the stated durations noticably only at extremely low system clock
frequencies.
Table 25
Flash Parameters (cont’d)
Parameter
Symbol
Values
Unit Note /
Test Condition
Min.
Typ.
Max.
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