參數(shù)資料
型號(hào)： SAF-XC2224L-20F66V
廠商： INFINEON TECHNOLOGIES AG
元件分類： 微控制器/微處理器
英文描述： 32-BIT, FLASH, 66 MHz, RISC MICROCONTROLLER, PQCC48
封裝： 0.50 MM PITCH, GREEN, PLASTIC, VQFN-48
文件頁(yè)數(shù)： 6/112頁(yè)
文件大?。?/td> 3122K
代理商： SAF-XC2224L-20F66V
XC2220L, XC2224L
XC2000 Family / Econo Line
Electrical Parameters
PRELIMINARY
Data Sheet
99
V1.0, 2010-12
Debug via JTAG
The following parameters are applicable for communication through the JTAG debug
interface. The JTAG module is fully compliant with IEEE1149.1-2000.
Note: These parameters are not subject to production test but verified by design and/or
characterization.
Note: Operating Conditions apply.
Table 36 is valid under the following conditions:
C
L= 20 pF; voltage_range= upper
Table 36
JTAG Interface Timing for Upper Voltage Range
Parameter
Symbol
Values
Unit Note /
Test Condition
Min.
Typ.
Max.
TCK clock period
t
1 SR
1001)
1) The debug interface cannot operate faster than the overall system, therefore
t
1 ≥ tSYS.
ns
2)
2) Under typical conditions, the JTAG interface can operate at transfer rates up to 10 MHz.
TCK high time
t
2 SR
16
ns
TCK low time
t
3 SR
16
ns
TCK clock rise time
t
4 SR
8ns
TCK clock fall time
t
5 SR
8ns
TDI/TMS setup to TCK
rising edge
t
6 SR
6
ns
TDI/TMS hold after TCK
rising edge
t
7 SR
6
ns
TDO valid from TCK falling
edge (propagation delay)3)
3) The falling edge on TCK is used to generate the TDO timing.
t
8 CC
29
32
ns
TDO high impedance to
valid output from TCK
falling edge4)3)
4) The setup time for TDO is given implicitly by the TCK cycle time.
t
9 CC
29
32
ns
TDO valid output to high
impedance from TCK
falling edge3)
t
10 CC
29
32
ns
TDO hold after TCK falling
t
18 CC
5
ns
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