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參數(shù)資料
| 型號： | SAF-C868-1SR |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, 40 MHz, MICROCONTROLLER, PDSO38 |
| 封裝： | PLASTIC, TSSOP-38 |
| 文件頁數(shù)： | 51/70頁 |
| 文件大?。?/td> | 1067K |
| 代理商： | SAF-C868-1SR |
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C868
Data Sheet
55
V 0.2, 2002-01
Power Saving Modes
The C868 provides two basic power saving modes, the idle mode and the power down
mode. Additionally, a slow down mode is available. This power saving mode reduces the
internal clock rate in normal operating mode and it can also be used for further power
reduction in idle mode.
Idle Mode
In the idle mode, the oscillator of the C868 continues to run, but the CPU is gated off
from the clock signal. However, the interrupt system, the serial port, the A/D converter,
the capture/compare unit, and all timers are further provided with the clock. The CPU
status is preserved in its entirety: the stack pointer, program counter, program status
word, accumulator, and all other registers maintain their data during idle mode.
Slow Down Mode
In some applications, where power consumption and dissipation are critical, the
controller might run for a certain time at reduced speed (for example, if the controller
is waiting for an input signal). Since in CMOS devices, there is an almost linear
dependence of the operating frequency and the power supply current, so, a reduction
of the operating frequency results in reduced power consumption.
Software Power Down Mode
In the software power down mode, the on-chip oscillator which operates with the XTAL
pins and the PLL are all stopped. Therefore, all functions of the microcontroller are
stopped and only the contents of the on-chip RAM, XRAM and the SFR's are
maintained. The port pins, which are controlled by their port latches, output the values
that are held by their SFR's. The port pins which serve the alternate output functions
show the values they had at the end of the last cycle of the instruction which initiated
the power down mode. ALE is held at logic low level or high impedance if disabled. In
the power down mode of operation, V
DDC and VDDP can be reduced to minimize power
consumption. It must be ensured, however, that V
DDC and VDDP is not reduced before
the power down mode is invoked, and that V
DDC and VDDP is restored to its normal
operating level before the power down mode is terminated. However, V
DDC cannot be
lower than V
DDP by more than 1(tbd) volt.
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