參數(shù)資料
型號(hào)： SAF-C868-1SR
廠商： INFINEON TECHNOLOGIES AG
元件分類： 微控制器/微處理器
英文描述： 8-BIT, 40 MHz, MICROCONTROLLER, PDSO38
封裝： PLASTIC, TSSOP-38
文件頁(yè)數(shù)： 11/70頁(yè)
文件大?。?/td> 1067K
代理商： SAF-C868-1SR
C868
Data Sheet
19
V 0.2, 2002-01
Reset and Brownout
The reset input is an active low input. An internal Schmitt trigger is used at the input for
noise rejection. The RESET pin must be held low for at least tbd usec. But the CPU will
only exit from reset condition after the PLL lock had been detected.
During RESET at transition from low to high, C868 will go into normal mode if ALE/BSL
is high and bootstrap loading mode if ALE/BSL is low. A pullup to VDDP or pulldown to
ground is recommended for pin ALE/BSL. TXD should have a pullup to VDDP and should
not be stimulated externally during reset, as a logic low at this pin will cause the chip to
go into test mode if ALE/BSL is low.
Figure 9 shows the possible reset circuits, note that the RESET pin does not have an
internal pullup resistance.
Figure 9
Reset Circuitries
An on-chip analog circuit detects brownout, if the supply voltage VDDC dips below the
threshold voltage VTHRESHOLD momentarily while RESET pin is high. If this detection is
active for tbd usec then the device will reset. When supply voltage VDDC recovers by
exceeding VTHRESHOLD while RESET is high, the reset is released once PLL is locked
for 4096 clocks. Bit BO in the PMCON0 register is set when brownout detected if
brownout detection was enabled, this bit is cleared by hardware reset RESET and
software. All ports are tristated during brownout.
The VTHRESHOLD has a nominal value of 1.47V, a minimum value of 1.1V and a
maximum value of 1.8V.
RESET
C868
a)
RESET
C868
&
RESET
C868
b)
c)
VDDP
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