參數(shù)資料
型號: SAF-C868-1RR
廠商: INFINEON TECHNOLOGIES AG
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 40 MHz, MICROCONTROLLER, PDSO38
封裝: PLASTIC, TSSOP-38
文件頁數(shù): 50/70頁
文件大?。?/td> 1067K
代理商: SAF-C868-1RR
C868
Data Sheet
54
V 0.2, 2002-01
SFR SCUWDT) consecutively. This double instruction sequence has been implemented
to increase system security.
It must be noted, however, that the watchdog timer is halted during the idle mode and
power-down mode of the processor (see section "Power Saving Modes"). It is not
possible to use the idle mode in combination with the watchdog timer function.
Therefore, even the watchdog timer cannot reset the device when one of the power
saving modes has been entered accidentally.
The time period for an overflow of the Watchdog Timer is programmable in two ways :
– the input frequency to the Watchdog Timer can be selected via bit WDTIN in
register WDTCON to be either f
SYS/2 or fSYS/128.
– the reload value WDTREL for the high byte of WDT can be programmed in register
WDTCON.
The period PWDT between servicing the Watchdog Timer and the next overflow can
therefore be determined by the following formula:
[0.1]
Table 14 lists the possible ranges for the watchdog time which can be achieved using a
certain module clock. Some numbers are rounded to 3 significant digits.
For safety reasons, the user is advised to rewrite WDTCON each time before the
Watchdog Timer is serviced.
Table 14
Watchdog Time Ranges
Reload value
in WDTREL
Prescaler for f
SYS
2 (WDTIN = ‘0’)
128 (WDTIN = ‘1’)
40 MHz
20 MHz
16 MHz
40 MHz
20 MHz
16 MHz
FFH
12.8 s
25.6 s
32.0 s
819.2 s 1.64 ms 2.05 ms
7FH
1.65 ms 3.3 ms
4.13 ms
105.7 ms 211.3 ms 264 ms
00H
3.28 ms 6.55 ms 8.19 ms 209.7 ms 419.4 ms 524 ms
PWDT =
f
SYS
2(1 +WDTIN*6) * (216 - WDTREL * 28)
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