參數(shù)資料
型號： SAB82526N
廠商： INFINEON TECHNOLOGIES AG
英文描述： Data Communications ICs
中文描述： 數(shù)據(jù)通信集成電路
文件頁數(shù)： 124/126頁
文件大小： 730K
代理商： SAB82526N
Semiconductor Group
124
SAB 82525
SAB 82526
SAF 82525
SAF 82526
The adaption of the AxCLKA/B pulses is solved by means of shifting the receive data and
transmit data in the ACFA device appropriately. In this case the AxCLKA and AxCLKB
synchronization pulses are also identical. The ACFA device contains special registers to
control the bit shift of the serial bit streams at the system interface (see ACFA Data Sheet).
With the following register programming the bit shift selected is T = – 510 for the HSCX
transmit data and T = 1 for the receive data respectively. The programming is as follows:
XDI:
XC1.XTO = 3D
H
=> X = 494
XC0.XCO = 07
H
RDO:
RC1.RTO = 00
H
=> X = 3
RC0. RCO = 03
H
The timing in principle is depicted in the following diagram. Without all details of a typical
electrical timing it illustrates how the different signals from HSCX, ACFA and PRACT are
mapped in such a Primary Access system.
=> T = – 510
=> T = 1
HSCX Signal Mapping for Primary Rate Interface T1/E1 Siemens System Interface
(ACFA/PRACT)
ITD05881
CLK4M
FSC
AxCLKA/B
RxCLKA/B
TxCLKA/B
TxDA/B
=
RxDA/B
=
=
=
=
XDI
RDO
FSC
CLK2M
(T
(T
=
=
-510)
1)
=:Channel 0,Bit 0 (Least Significant Bit)
ACFA Programming for Appropriate Delays (see ACFA Data Sheet):
XDI :
RDO :
T = - 510 = > X = 495 = > XC1.XTO = 3D
RC1.RTO
>
=
3
=
X
>
=
1
=
T
XC0.XCO = 7
3
=
H
RC0.RCO
0
=
,
H
H
,
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