參數(shù)資料
型號: SAB-C161S-L25M
廠商: INFINEON TECHNOLOGIES AG
元件分類: 微控制器/微處理器
英文描述: 16-BIT, 25 MHz, MICROCONTROLLER, PQFP80
封裝: PLASTIC, MQFP-80
文件頁數(shù): 43/75頁
文件大?。?/td> 1315K
代理商: SAB-C161S-L25M
C161S
Timing Characteristics
Data Sheet
44
V1.0, 2003-11
5
Timing Characteristics
5.1
Definition of Internal Timing
The internal operation of the C161S is controlled by the internal CPU clock
f
CPU. Both
edges of the CPU clock can trigger internal (e.g. pipeline) or external (e.g. bus cycles)
operations.
The specification of the external timing (AC Characteristics) therefore depends on the
time between two consecutive edges of the CPU clock, called “TCL” (see Figure 10).
Figure 10
Generation Mechanisms for the CPU Clock
The CPU clock signal
f
CPU can be generated from the oscillator clock signal fOSC via
different mechanisms. The duration of TCLs and their variation (and also the derived
external timing) depends on the used mechanism to generate
f
CPU. This influence must
be regarded when calculating the timings for the C161S.
Note: The example for PLL operation shown in Figure 10 refers to a PLL factor of 4.
The used mechanism to generate the basic CPU clock is selected by bitfield CLKCFG
in register RP0H.7-5. Upon a long hardware reset register RP0H is loaded with the logic
MCT04338
f
OSC
f
CPU
Phase Locked Loop Operation
TCL
f
OSC
f
CPU
Direct Clock Drive
f
OSC
f
CPU
Prescaler Operation
TCL
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