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參數(shù)資料
| 型號(hào)： | SAA7710T |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | High Quality Audio-Performance Digital Add-On Processor For Digital Sound Systems.(應(yīng)用在數(shù)字聲音系統(tǒng)的高品質(zhì)音頻性能數(shù)字附加處理器) |
| 中文描述： | 高品質(zhì)音頻高性能數(shù)字加到了數(shù)字音響系統(tǒng)。（應(yīng)用在數(shù)字聲音系統(tǒng)的高品質(zhì)音頻性能數(shù)字附加處理器處理器） |
| 文件頁數(shù)： | 9/28頁 |
| 文件大?。?/td> | 187K |
| 代理商： | SAA7710T |
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1998 Mar 13
9
Philips Semiconductors
Product specification
Dolby* Pro Logic Surround;
Incredible Sound
SAA7710T
Table 1
Data Accuracy in I
2
S-bus Interface
INCOMING DATA WIDTH
I
2
S-BUS IN DATA WIDTH
I
2
S-BUS OUT DATA WIDTH
A < 18
B
≥
18
A
18
A
18
T
HE
I
2
S-
BUS OUTPUT INTERFACE
The I
2
S-bus data output interfaces (see Fig.1) I
2
S OUT 1,
I
2
S OUT 2 and I
2
S OUT 3 use the same I
2
S-bus data
signals which are selected by the input switch circuit. The
I
2
S-bus WS and BCK output signals remain in phase with
the external input signals at all times. The output data is
1/f
s
cycle delayed relative to the input data. The selected
word-select and bit-clock are included as part of the output
interface: I
2
S_WSOUT, I
2
S_BCKOUT. These two output
signals can be 3-stated by setting the DIS_BCKWS bit
(see Table 4). The 3-state output of the I
2
S_DATAOUT3
signal can be enabled by setting the ENA_I
2
S3 bit (see
Table 4).
The timing diagram of the I
2
S-bus outputs is shown in
Fig.6. The timing details can be found in Chapter “AC
characteristics”.
Fig.6 Timing diagram of I
2
S-bus output interface.
handbook, full pagewidth
MGE755
tHC
tLC
td1
tf
tr
tf
tr
td3
tf
tr
ts2
td2
tacc
CL
WS
DATA (in)
DATA (out)
DATA VALID
MSB
MSB
I
2
S_BCKIN1, 2
I
2
S_BCKOUT
I
2
S_WSIN1, 2
I
2
S_WSOUT
I
2
S_DATAIN1, 2
I
2
S_DATAOUT1, 2, 3
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相關(guān)代理商/技術(shù)參數(shù) |
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| SAA7710T/N104 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Dolby* Pro Logic Surround; Incredible Sound |
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| SAA7715H | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Digital Signal Processor |
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