- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄372115 > SAA7707H (NXP SEMICONDUCTORS) Shaft; Style: 1 - light; Applicable Model: LE-P / LEL-W PDF資料下載
參數(shù)資料
| 型號： | SAA7707H |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | Shaft; Style: 1 - light; Applicable Model: LE-P / LEL-W |
| 中文描述： | 0-BIT, 36.86 MHz, OTHER DSP, PQFP80 |
| 封裝： | 14 X 20 MM, 2.80 MM HEIGHT, PLASTIC, SOT-318-2, QFP-80 |
| 文件頁數(shù)： | 22/48頁 |
| 文件大?。?/td> | 244K |
| 代理商： | SAA7707H |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁當前第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁
1997 May 30
22
Philips Semiconductors
Preliminary specification
Car radio Digital Signal Processor (CDSP)
SAA7707H
To minimise electro magnetic interference (EMI), the
output has to be disabled if the output is not used.
The timing diagram of the communication is illustrated in
Fig.13.
10.5
Relationship between external input and
external output
The stereo decoder output has an internal I
2
S-bus format
with 32 clock pulses per channel for 18 valid and 14 zero
data bits. Providing that the stereo decoder output is used,
the communication with the external processor will also
have 32 clock pulses per channel for 18 valid and 14 zero
data bits.
When an external digital source is selected, the number of
valid bits and clock pulses of this source determines the
output to the external processor. This relationship is
shown in Table 5.
Table 5
Relationship between external input and
external output.
10.6
RDS decoder (RDSCLK and RDSDAT)
The RDS decoder recovers the additional inaudible RDS
information transmitted by FM radio broadcasting.
The (buffered) data is provided as an output for further
processing by a suitable decoder. The operational
functions of the decoder are in accordance with EBU
specification EN 50067
The RDS decoder has three different functions:
1.
Clock and data recovery from the MPX signal
2.
Buffering of 16 bits, if selected
3.
Interfacing with the microcontroller.
10.7
Clock and data recovery
The RDS chain has a separate input. This enables RDS
updates during tape play and also the use of a second
receiver for monitoring the RDS information of signals from
another transmitter (double tuner concept).
INPUT
CLOCK
BITS
INPUT
DATA
BITS
≥
18
≥
18
<18
<18
OUTPUT
CLOCK
BITS
OUTPUT
DATA
BITS
>32
32
18
18
18
≥
18 and
≤
32
≥
18 and
≤
32
<18
as input
as input
as input
as input
In this way, it can be performed without interruption of the
audio program. The MPX signal from the main tuner of the
car radio can be connected to this RDS input via the
built-in source selector.
The input selection is controlled by the input selector
control register.
For FM stereo reception, the clock of the total chip is
locked to the stereo pilot (19 kHz multiple). For FM mono,
the DCS loop keeps the DCS clock around the same
19 kHz multiple. In all other cases, such as AM reception
or tape, the DCS circuit has to be set to a preset position.
Under these conditions, the RDS system is always clocked
by the DCS clock in a 38 kHz (4
×
9.5 kHz) based
sequence.
10.8
Timing of clock and data signals
The timing of the clock and data output is derived from the
incoming data signal. Under stable conditions, the data will
remain valid for 400
μ
s after the clock transition.
The timing of the data change is 100
μ
s before a positive
clock change. This timing is suitable for positive and
negative triggered interrupts on a microcontroller.
The RDS timing is illustrated in Fig.14.
During poor reception, it is possible that errors in phase
may occur. Consequently the duty cycle of the clock and
data signals will vary from a minimum of 0.5 times to a
maximum of 1.5 times the standard clock periods.
Normally, errors in phase do not occur on a cyclic basis.
10.9
Buffering of RDS data
The repetition frequency of RDS data is approximately
1187 Hz. This results in an interrupt on the microcontroller
every 842
μ
s. In a second mode, the RDS interface has a
double 16-bit buffer.
10.10 Buffer interface
The RDS interface buffers 16 data bits. Each time 16 bits
are received, the data line is pulled down and the buffer is
overwritten. The control microcontroller has to monitor the
input data line at least every 13.5 ms. This mode is
selected by the input selector control register.
The interface signals from the RDS decoder and the
microcontroller in the buffer mode are illustrated in Fig.15.
When the buffer is filled with 16 bits, the data line is pulled
down.
The data line will remain LOW until reading from the buffer
is started, by pulling down the clock line. The first data bit
is clocked out.
相關PDF資料 |
PDF描述 |
|---|---|
| SAA7710T | High Quality Audio-Performance Digital Add-On Processor For Digital Sound Systems.(應用在數(shù)字聲音系統(tǒng)的高品質音頻性能數(shù)字附加處理器) |
| SAA7715AH | Digital Signal Processor |
| SAA7715 | Digital Signal Processor |
| SAA7715H | Digital Signal Processor |
| SAA7740 | Digital Audio Processing IC DAPIC |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| SAA7708H | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Car Radio Digital Signal Processor |
| SAA7709/N107 | 制造商:PHILIPS-SEMI 功能描述: |
| SAA7709H/N103 | 功能描述:音頻 DSP DIGITAL SIGNAL PROCESSOR RoHS:否 制造商:Texas Instruments 工作電源電壓: 電源電流: 工作溫度范圍: 安裝風格: 封裝 / 箱體: 封裝:Tube |
| SAA7709H/N103,518 | 功能描述:音頻 DSP DIRAC-2 RoHS:否 制造商:Texas Instruments 工作電源電壓: 電源電流: 工作溫度范圍: 安裝風格: 封裝 / 箱體: 封裝:Tube |
| SAA7709H/N103,557 | 功能描述:音頻 DSP DIGITAL SIGNAL RoHS:否 制造商:Texas Instruments 工作電源電壓: 電源電流: 工作溫度范圍: 安裝風格: 封裝 / 箱體: 封裝:Tube |
發(fā)布緊急采購，3分鐘左右您將得到回復。