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參數(shù)資料
| 型號(hào)： | SAA7707H |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 數(shù)字信號(hào)處理 |
| 英文描述： | Shaft; Style: 1 - light; Applicable Model: LE-P / LEL-W |
| 中文描述： | 0-BIT, 36.86 MHz, OTHER DSP, PQFP80 |
| 封裝： | 14 X 20 MM, 2.80 MM HEIGHT, PLASTIC, SOT-318-2, QFP-80 |
| 文件頁數(shù)： | 21/48頁 |
| 文件大?。?/td> | 244K |
| 代理商： | SAA7707H |
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1997 May 30
21
Philips Semiconductors
Preliminary specification
Car radio Digital Signal Processor (CDSP)
SAA7707H
10 I
2
S-BUS DESCRIPTION
10.1
I
2
C-bus control (pins SCL and SDA)
For external control of the SAA7707H, a standard I
2
C-bus
is implemented. There are two different types of control
instructions:
Instructions to control the DSP program, programming
the coefficient RAM and reading the values of
parameters (level, multi-path etc.)
Instructions controlling the DATA flow, such as source
selection, IAC control and clock speed.
10.2
I
2
S-bus description
For communication with external digital sources and/or
additional external processors, the I
2
S-bus digital interface
is used. It is a serial 3-line bus, having one line for Serial
Data (SD), one line for Serial Clock (SCK) and one line for
the Word Select (WS). For external processors, the CDSP
acts as a master transmitter; for external digital sources
the CDSP acts as a slave. The communication with the
external processor and external digital sources are
separated, to allow both features at the same time.
Figure 12 shows an extract of the Philips I
2
S-bus
specification interface report regarding the general timing
and format of the I
2
S-bus. Word select logic 0 means left
channel word; word select logic 1 means right channel
word.
The serial data is transmitted in twos complement with the
MSB first. One clock period after the negative edge of the
Word Select line, the MSB of the left channel is
transmitted. Data is synchronized with the negative edge
of the clock and latched at the positive edge.
As inputs from an external processor for the four audio
channels, two data lines have been implemented.
10.3
Communication with external digital audio
sources (DCC + CD-WS/CL/Data pins)
For communication with external digital audio sources, two
additional I
2
S-bus inputs are available. They each have
clock, data and Word Select input lines with a maximum
useful data length of 18 bits. The external source is master
and supplies the clock. The input selection and port
selection is controllable via the input selector control
register. The DSP program is synchronized with the
external source via the Word Select signal.
The input allows a variety of clock frequencies, sample
frequencies and word lengths.
The Word Select line automatically determines the
SAA7707H sampling frequency.
Using the Digital Source Selector (see Fig.1), one of the
three possible input sources is selected. The selected
audio data channels are input to two 18-bit wide memory
mapped I/O registers of the DSP named Input Left and
Input Right.
Except for the 4f
as
pulse to control the upsample filter
(see Section 9.2), other synchronization signals such as
internal Word Select are derived from the I
2
S-bus input
signals.
The input bit clock is used as a bit clock for the external
processor. As a consequence, a clock pulse input signal
with less than 18 bits will result in a communication with an
external processor of the same number of bits. In this
event, the trailing bits of the 18-bit input registers will be
zero.
If the I
2
S-bus driver outputs of the external digital source
ICs have 3-state outputs, they can all be connected on one
single I
2
S-bus input.
10.4
Communication with external processors and
other devices (EXWS/CL/EXDAT1 and EXDAT2)
For communication with external processors, delay lines
or other I
2
S-bus controllable devices, a complete
dual-channel 18-bit output bus is implemented.
The SAA7707H acts as the master transmitter and the
external device has to be synchronized with the Word
Select line.
As input for the processed data, two data input lines have
been implemented that are processed synchronously with
the data output to the external processor (see Table 4).
This enables, in total, a feedback of two stereo audio
channels.
For this communication, the DSP core has the following
18-bit memory mapped I/O registers available:
Table 4
DSP core I/O registers
The DSP program moves data from the two external
I
2
S-bus data output registers to the external processor and
reads it back from the two or four external I
2
S-bus data
input registers. The hardware of the bus can be enabled by
the input control register.
INPUT
OUTPUT
EXDAT1 left/right
EXDAT2 left/right
EXDAT left/right
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SAA7708H | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Car Radio Digital Signal Processor |
| SAA7709/N107 | 制造商:PHILIPS-SEMI 功能描述: |
| SAA7709H/N103 | 功能描述:音頻 DSP DIGITAL SIGNAL PROCESSOR RoHS:否 制造商:Texas Instruments 工作電源電壓: 電源電流: 工作溫度范圍: 安裝風(fēng)格: 封裝 / 箱體: 封裝:Tube |
| SAA7709H/N103,518 | 功能描述:音頻 DSP DIRAC-2 RoHS:否 制造商:Texas Instruments 工作電源電壓: 電源電流: 工作溫度范圍: 安裝風(fēng)格: 封裝 / 箱體: 封裝:Tube |
| SAA7709H/N103,557 | 功能描述:音頻 DSP DIGITAL SIGNAL RoHS:否 制造商:Texas Instruments 工作電源電壓: 電源電流: 工作溫度范圍: 安裝風(fēng)格: 封裝 / 箱體: 封裝:Tube |
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