參數(shù)資料
型號(hào): SAA7373GP
廠商: NXP SEMICONDUCTORS
元件分類(lèi): 消費(fèi)家電
英文描述: Digital servo processor and Compact Disc decoder CD7
中文描述: SPECIALTY CONSUMER CIRCUIT, PQFP64
文件頁(yè)數(shù): 12/60頁(yè)
文件大小: 323K
代理商: SAA7373GP
1998 Jul 06
12
Philips Semiconductors
Product specification
Digital servo processor and Compact Disc
decoder (CD7)
SAA7373
7.5
Subcode data processing
7.5.1
Q-
CHANNEL PROCESSING
The 96-bit Q-channel word is accumulated in an internal
buffer. The last 16 bits are used internally to perform a
Cyclic Redundancy Check (CRC). If the data is good, the
SUBQREADY-I signal will go LOW. SUBQREADY-I can
be read via the SDA or STATUS pins, selected via
register 2. Good Q-channel data may be read from SDA.
7.5.2
EIAJ 3
AND
4-
WIRE SUBCODE
(CD
GRAPHICS
)
INTERFACES
Data from all the subcode channels (P-to-W) may be read
via the subcode interface, which conforms to
EIAJ CP-2401. The interface is enabled and configured as
either a 3-wire or 4-wire interface via register F. The
subcode interface output formats are illustrated in Fig.7,
where the RCK signal is supplied by another device such
as a CD graphics decoder.
7.5.3
V4
SUBCODE INTERFACE
Data of subcode channels, Q-to-W, may be read via pin V4
if selected via register D. The format is similar to RS232
and is illustrated in Fig.8. The subcode sync word is
formed by a pause of (200/n)
μ
s minimum. Each subcode
byte starts with a logic 1 followed by 7 bits (Q-to-W). The
gap between bytes is variable between (11.3/n)
μ
s and
(90/n)
μ
s.
The subcode data is also available in the EBU output
(DOBM) in a similar format.
Fig.7 EIAJ subcode (CD graphics) interface format.
handbook, full pagewidth
SBSY
SFSY
RCK
SUB
SFSY
RCK
SUB
SFSY
RCK
SUB
EIAJ 4-wire subcode interface
EIAJ 3-wire subcode interface
SF0
SF1
SF2
SF3
SF97
SF0
SF1
P-W
P-W
P-W
P-W
P-W
P-W
P
Q
R
S
T
U
V
W
MBG410
SF0
SF1
SF2
SF3
SF97
SF0
SF1
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