參數(shù)資料
型號: SAA7335GP
廠商: NXP SEMICONDUCTORS
元件分類: 消費家電
英文描述: DSP for CD and DVD-ROM systems
中文描述: SPECIALTY CONSUMER CIRCUIT, PQFP100
封裝: 14 X 14 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-407-1, LQFP-100
文件頁數(shù): 26/36頁
文件大?。?/td> 196K
代理商: SAA7335GP
1997 Aug 11
26
Philips Semiconductors
Preliminary specification
DSP for CD and DVD-ROM systems
SAA7335
Notes
1.
2.
Timing reference voltage levels are 0.8 V and V
DDD
0.8 V.
Negative set-up time means that data may change after clock transition.
External RAM timing
(see Figs 18 and 20)
t
AV-DV
t
OE-DV
t
W(W)
t
su(A)
t
h(A)
t
su(D-EW)
t
h(D-EW)
t
OE-DA
t
OD-DI
address valid to data valid
output enable to data valid
write pulse width
address set-up before start of write
address hold after end of write
data set-up to end of write
data hold after end of write
output enable to data active
output disable to data inactive
tbf
tbf
tbf
tbf
tbf
tbf
tbf
tbf
tbf
ns
ns
ns
ns
ns
ns
ns
ns
ns
Microcontroller interface timing
(see Figs 18 and 20)
I
NPUT
ALE
t
su(A-ALE)
t
h(A-ALE)
t
ALEL
address set-up before ALE LOW
address hold after ALE LOW
input LOW time
25
25
1
×
ADC
CLK + 15
1
×
ADC
CLK + 15
ns
ns
ns
t
ALEH
input HIGH time
ns
t
d(ALEL-WRL)
t
r
t
f
I
NPUTS
RD
I AND
WR
I
delay time ALE LOW to WR LOW
rise time
fall time
240
ns
ns
ns
t
IL(R/W)
input LOW time
1
×
ADC
CLK + 15
1
×
ADC
CLK + 15
ns
t
IH(R/W)
input HIGH time
ns
t
r
t
f
R
EAD MODE
rise time
fall time
240
ns
ns
t
d(RLDV)
delay time RD LOW to DA0 to DA7
valid
delay time RD HIGH to DA0 to DA7
high-impedance
2
×
ADC
CLK + 35
15
ns
t
d(RHDX)
ns
W
RITE MODE
t
su(QVWX)
set-up time WR LOW to
DA0 to DA7
hold time WR HIGH to DA0 to DA7
3-state
ns
t
h(WHQX)
2
×
ADC
CLK + 25
ns
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
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