參數(shù)資料
型號: SAA7335GP
廠商: NXP SEMICONDUCTORS
元件分類: 消費家電
英文描述: DSP for CD and DVD-ROM systems
中文描述: SPECIALTY CONSUMER CIRCUIT, PQFP100
封裝: 14 X 14 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-407-1, LQFP-100
文件頁數(shù): 21/36頁
文件大?。?/td> 196K
代理商: SAA7335GP
1997 Aug 11
21
Philips Semiconductors
Preliminary specification
DSP for CD and DVD-ROM systems
SAA7335
Flags output (CFLG) (open-drain output)
A 1-bit flag signal is available at the CFLG pin, this contains 11 bits running off the ADCCLK, each bit period is 7 ADCCLK
periods. This signal shows the status of the error corrector and interpolator and is updated every frame.
Table 6
Definition of flag bits
Notes
1.
2.
3.
4.
For DVD mode read PI for C1 and PO for C2.
This flag refers to the previous correction frame.
This flag refers to the previous correction frame (is not valid i.e. always logic 0 in DVD mode).
Bit order of root count is 9, then 6 to 8 for root count (3 to 0).
A
BSOLUTE TIME SYNC
The sync signal is the absolute time sync signal. In the CD mode it is the FIFO-passed subcode sync and relates the
position of the subcode sync to the audio data (DAC output). In the DVD mode it indicates the start of a new sector
header.
The flag may be used for special purposes such as synchronization of different players.
BIT
NUMBER
VALUE
DESCRIPTION
0
1
START bit
C1 first or C1 last; note 1
C2 first, CD mode reserved, DVD mode; note 1
reserved; note 1
C2 last; note 1
corrector not active; note 1
1 to 3
000
001
010
011
100
all others reserved
core fail
4
5
failure flag set because correction impossible; note 2
flag fail; note 3
this indicates the number of errors corrected; note 4
STOP bit
9, 6 to 8
10
root count (3 to 0)
0
Fig.16 Flags output format.
handbook, halfpage
START
bit
data bits
pause
MGK252
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