2004 Apr 05
7
Philips Semiconductors
Product specification
XGA analog input flat panel controller
SAA6713AH
SDA
SCL
RESERVED2
RESERVED3
V
SSD(IC4)
V
DDD(IC4)
CLK
V
SSD(EP1)
V
DDD(EP1)
INT
RST
PCLK
CSG0
CSG1
CSG2/A0
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
I/O
I
I
O
I
O
O
O
I/O
serial data input or output (I
2
C-bus)
serial clock input (I
2
C-bus)
connect with a pull-up resistor of 4.7 k
to V
DDE
(3.3 or 5 V)
connect with a pull-up resistor of 4.7 k
to V
DDE
(3.3 or 5 V)
internal digital core supply ground 4
internal digital core supply voltage 4 (2.5 V)
master clock input
external digital pad supply ground 1
external digital pad supply voltage 1 (3.3 V)
microcontroller interrupt output (active LOW)
master reset input (active LOW)
panel clock output
control signal generator 0 output
control signal generator 1 output
control signal generator 2 output (CSG2) or I
2
C-bus slave address input, latched
via hardware reset (A0)
external digital pad supply ground 2
external digital pad supply voltage 2 (3.3 V)
panel data port A bit 0
panel data port A bit 1
panel data port A bit 2
panel data port A bit 3
panel data port A bit 4
panel data port A bit 5
panel data port A bit 6
panel data port A bit 7
external digital pad supply ground 3
external digital pad supply voltage 3 (3.3 V)
panel data port B bit 0
panel data port B bit 1
internal digital core supply ground 5
internal digital core supply voltage 5 (2.5 V)
panel data port B bit 2
panel data port B bit 3
panel data port B bit 4
panel data port B bit 5
panel data port B bit 6
panel data port B bit 7
external digital pad supply ground 4
external digital pad supply voltage 4 (3.3 V)
panel data port C bit 0
V
SSD(EP2)
V
DDD(EP2)
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
V
SSD(EP3)
V
DDD(EP3)
PB0
PB1
V
SSD(IC5)
V
DDD(IC5)
PB2
PB3
PB4
PB5
PB6
PB7
V
SSD(EP4)
V
DDD(EP4)
PC0
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
SYMBOL
PIN
(1)
TYPE
DESCRIPTION