參數(shù)資料
型號(hào): SAA6713AH
廠商: NXP Semiconductors N.V.
英文描述: XGA analog input flat panel controller
中文描述: 模擬輸入的XGA液晶控制器
文件頁(yè)數(shù): 17/100頁(yè)
文件大?。?/td> 498K
代理商: SAA6713AH
2
1
P
P
X
S
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Table 9
Mode detection configuration registers (page 2); note 1
Note
1.
X = don’t care.
ADC_G_CON
ADC_B_BRI
ADC_B_CON
04H
05H
06H
W
W
W
00H
00H
00H
adc_green_contrast[7:0]
adc_blue_brightness[7:0]
adc_blue_contrast[7:0]
REGISTER
ADR R/W
RESET
D7
D6
D5
D4
D3
D2
D1
D0
Mode detection: 00H to 0EH
MD_CTRL
00H
W
000 0000
no_vsync_
int_en
clear_int
int_lock
delay_
vsync
no_hsync_
int_en
vsync_pol
h_clocks_
accu
vsync_int_
en
hsync_pol
h_clocks_
cont
vsync_pol_
int_en
no_vsync
md_on
MD_INT_EN
01H
W
0000 0000 jitter_int_en v_lines_
int_en
v_clocks_
int_en
h_clocks_
int_en
jitter_
detected
hsync_pol_
int_en
no_hsync
MD_POL
02H
R
0 0011
MD_V_LINE_HI
MD_V_LINE_LO
MD_H_CLK_HI
MD_H_CLK_LO
MD_V_CLK_HI
MD_V_CLK_MD
MD_V_CLK_LO
MD_INT_HI
03H
04H
05H
06H
07H
08H
09H
0AH R
R
R
R
R
R
R
R
000
00H
00H
00H
00H
00H
00H
00 0000
v_lines[10:8]
v_lines[7:0]
h_clocks[15:8]
h_clocks[7:0]
v_clocks[23:16]
v_clocks[15:8]
v_clocks[7:0]
vsync_int
jitter_int
vsync_pol_
int
hsync_pol_
int
v_lines_int
no_vsync_
int
h_clocks_
int
avs_act_int ahs_act_int
no_hsync_
int
v_clocks_
int
MD_INT_LO
0BH R
000
MD_ACT_INT
0CH R
X000 0000 reserved
reserved
reserved
reserved
asog_act_
int
asog_
active
asog_int_
en
acsvs_act_
int
acsvs_
active
acsvs_int_
en
MD_SYNC_ACT
0DH R
00 0000
reserved
reserved
avs_active
ahs_active
MD_ACT_IEN
0EH W
0000 0000 reserved
reserved
reserved
reserved
avs_int_en ahs_int_en
REGISTER
ADR R/W
RESET
D7
D6
D5
D4
D3
D2
D1
D0
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