參數(shù)資料
型號(hào): SAA5500PS/NNNN
廠商: NXP SEMICONDUCTORS
元件分類: 微控制器/微處理器
英文描述: 8-BIT, OTPROM, 12 MHz, MICROCONTROLLER, PDIP52
封裝: 0.600 INCH, PLASTIC, SDIP-52
文件頁數(shù): 48/80頁
文件大?。?/td> 340K
代理商: SAA5500PS/NNNN
1999 Oct 27
52
Philips Semiconductors
Preliminary specication
Standard TV microcontrollers with
On-Screen Display (OSD)
SAA55xx
19 DISPLAY
The display section is based on the requirements for a
Level 1.5 WST Teletext. There are some enhancements
for use with locally generated OSDs.
The display section reads the contents of the Display
memory and interprets the control/character codes. From
this information and other global settings, the display
produces the required RGB signals and Video/Data (Fast
Blanking) signal for a TV signal processing device.
The display is synchronised to the TV signal processing
device by way of horizontal and vertical sync signals
provided by external circuits (Slave Sync mode). From
these signals all display timings are derived.
19.1
Display features
Teletext and Enhanced On-Screen Display (OSD)
modes
Level 1.5 WST features
Single/Double/Quadruple Width and Height for
characters
Variable flash rate controlled by software
Fixed character matrix (H × V) 12 × 10
Soft colours using Colour Look Up Table (CLUT) with
4096 colour palette
Fringing (Shadow) selectable from N-S-E-W direction
Fringe colour selectable
Meshing of defined area
Contrast reduction of defined area
Cursor
1 WST Character set (G0/G2) in single device (e.g.
Latin or Cyrillic or Greek or Arabic)
G1 Mosaic graphics, Limited G3 Line drawing
characters.
Fig.22 Display block diagram.
handbook, full pagewidth
MICROPROCESSOR
INTERFACE
DISPLAY
TIMING
HSYNC
CLK
VSYNC
CHARACTER
FONT
ADDRESSING
address
data
address
data
address
data
control
to memory interface
from memory interface
FUNCTION
REGISTERS
PARALLEL/SERIAL
CONVERTER
AND FRINGING
ATTRIBUTE
HANDLING
CLUT RAM
DISPLAY DATA
ADDRESSING
MBK965
CHARACTER
ROM
AND
DRCs
DATA
BUFFER
DAC
GB
FB
R
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